公开(公告)号：US20170069827A1

公开(公告)日：2017-03-09

申请号：US15131564

申请日：2016-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Kyu LEE ,  Gwan-hyeob KOH ,  Hong-kook MIN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L27/228 ,  H01L27/20 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

Abstract translation: 一种半导体装置，包括基板，逻辑区域上的第一绝缘层和基板的存储区域，第一绝缘层上的第二绝缘层，位于逻辑区域之间的第一绝缘层和第二绝缘层之间的基极绝缘层 存储区域，通过第一绝缘层的第一互连结构，穿过第二绝缘层的第二互连结构，在逻辑区域上穿过基极绝缘层的基底互连结构，以及基极绝缘层中的可变电阻结构， 存储区域。 可变电阻结构包括依次堆叠的下电极，磁阻器件和上电极。 下电极和上电极分别在存储区域上电连接到第一互连结构中的一个和第二互连结构中的一个。