公开(公告)号：US09954030B2

公开(公告)日：2018-04-24

申请号：US15131564

申请日：2016-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-kyu Lee ,  Gwan-hyeob Koh ,  Hong-kook Min

IPC: H01L27/22 ,  H01L43/08 ,  H01L27/20 ,  H01L43/10

CPC classification number: H01L27/228 ,  H01L27/20 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

公开(公告)号：US10566385B2

公开(公告)日：2020-02-18

申请号：US15925043

申请日：2018-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-kyu Lee ,  Gwan-hyeob Koh ,  Hong-kook Min

IPC: H01L27/22 ,  H01L27/20 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

公开(公告)号：US20180211996A1

公开(公告)日：2018-07-26

申请号：US15925043

申请日：2018-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-kyu LEE ,  Gwan-hyeob Koh ,  Hong-kook Min

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L27/20

CPC classification number: H01L27/228 ,  H01L27/20 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.