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公开(公告)号：US10777276B2
公开(公告)日：2020-09-15
申请号：US16533143
申请日：2019-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-woo Kim , Jae-kyu Lee , Ki-seok Suh , Hyeong-sun Hong , Yoo-sang Hwang , Gwan-hyeob Koh
IPC: H01L23/528 , G11C14/00 , H01L45/00 , H01L29/08 , H01L27/108 , H01L29/423 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/24 , H01L27/22 , H01L27/105 , H01L27/02 , G11C7/10 , G11C11/00
Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.
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公开(公告)号：US10566385B2
公开(公告)日：2020-02-18
申请号：US15925043
申请日：2018-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong-kyu Lee , Gwan-hyeob Koh , Hong-kook Min
Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.
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公开(公告)号：US20180211996A1
公开(公告)日：2018-07-26
申请号：US15925043
申请日：2018-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong-kyu LEE , Gwan-hyeob Koh , Hong-kook Min
CPC classification number: H01L27/228 , H01L27/20 , H01L27/222 , H01L43/08 , H01L43/10
Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.
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公开(公告)号：US20180204867A1
公开(公告)日：2018-07-19
申请号：US15676069
申请日：2017-08-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dae-shik Kim , Gwan-hyeob Koh
IPC: H01L27/146 , H01L23/00 , H04N5/378 , H04N5/78 , H04N5/353 , H04N5/3745 , H04N9/07 , H04N9/04
CPC classification number: H01L27/14634 , H01L24/80 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14645 , H01L27/1469 , H01L2224/80895 , H01L2924/1431 , H01L2924/1443 , H01L2924/146 , H04N5/3532 , H04N5/37455 , H04N5/378 , H04N5/78 , H04N5/907 , H04N9/045 , H04N9/07 , H04N2209/042
Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.
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公开(公告)号：US10580979B2
公开(公告)日：2020-03-03
申请号：US16109914
申请日：2018-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Il-mok Park , Gwan-hyeob Koh , Dae-hwan Kang
Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.
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Patent Agency Ranking
公开(公告)号：US10263040B2
公开(公告)日：2019-04-16
申请号：US15906550
申请日：2018-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/24 , H01L27/102 , H01L45/00 , H01L21/20 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US09991315B2
公开(公告)日：2018-06-05
申请号：US15632969
申请日：2017-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki Terai , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/00 , H01L27/24 , H01L45/00 , H01L27/06 , G11C13/00 , H01L27/10 , H01L27/11582 , H01L43/08
CPC classification number: H01L27/2427 , G11C11/1659 , G11C13/0002 , G11C13/003 , G11C2213/17 , G11C2213/71 , G11C2213/76 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L43/08 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1675
Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
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公开(公告)号：US10651236B2
公开(公告)日：2020-05-12
申请号：US16392969
申请日：2019-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kil-ho Lee , Yoon-jong Song , Gwan-hyeob Koh
Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.
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公开(公告)号：US09954030B2
公开(公告)日：2018-04-24
申请号：US15131564
申请日：2016-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong-kyu Lee , Gwan-hyeob Koh , Hong-kook Min
CPC classification number: H01L27/228 , H01L27/20 , H01L27/222 , H01L43/08 , H01L43/10
Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.
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公开(公告)号：US09741764B1
公开(公告)日：2017-08-22
申请号：US15257609
申请日：2016-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Masayuki Terai , Gwan-hyeob Koh , Dae-hwan Kang
CPC classification number: H01L27/2427 , G11C11/1659 , G11C13/0002 , G11C13/003 , G11C2213/17 , G11C2213/71 , G11C2213/76 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L43/08 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1675
Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.
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