公开(公告)号：US20240357802A1

公开(公告)日：2024-10-24

申请号：US18525235

申请日：2023-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Hui Jung KIM

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor memory device comprising: a substrate including active patterns; a gate structure intersecting the active patterns; bit-line structures on the substrate; first contacts, wherein the bit-line structures and the first contacts are alternately arranged with each other; insulating patterns respectively disposed on the bit-line structures, wherein an insulating pattern among the insulating patterns is disposed in a first trench exposing a sidewall of a first contact among the first contacts and at least a portion of the gate structure; and second contacts disposed on the first contacts, wherein a second contact among the second contacts is disposed in a second trench exposing a sidewall of the insulating pattern and an upper surface of the first contact, wherein the insulating pattern overlaps an upper surface of a bit-line structure among the bit-line structures and extends along sidewalls of the first and second trenches and contacts the first and second contacts.

公开(公告)号：US20210013212A1

公开(公告)日：2021-01-14

申请号：US17037851

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Sub KIM ,  Hui Jung KIM ,  Myeong Dong LEE ,  Jin Hwan CHUN

IPC: H01L27/108 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

公开(公告)号：US20200381619A1

公开(公告)日：2020-12-03

申请号：US16998542

申请日：2020-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Chang Seok KANG ,  Yong Seok KIM ,  Kohji KANAMORI ,  Hui Jung KIM ,  Jun Hee LIM

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/102

Abstract: A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

公开(公告)号：US20190326511A1

公开(公告)日：2019-10-24

申请号：US16172830

申请日：2018-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan LEE ,  Chang Seok KANG ,  Yong-Seok KIM ,  Kohji KANAMORI ,  Hui Jung KIM ,  Jun Hee LIM

IPC: H01L45/00 ,  H01L27/102 ,  H01L27/24

Abstract: A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.