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    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240188293A1

    公开(公告)日：2024-06-06

    申请号：US18229296

    申请日：2023-08-02

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sam Ki KIM ,  Nam Bin KIM ,  Ji Woong KIM ,  Tae Hun KIM ,  Ki Bong MOON ,  Sae Rom LEE ,  Sung-Bok LEE ,  Jun Hee LIM ,  Nag Yong CHOI ,  Sun Gyung HWANG

    IPC分类号： H10B43/27 ,  H10B43/40

    CPC分类号： H10B43/27 ,  H10B43/40

    摘要： A semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210249397A1

    公开(公告)日：2021-08-12

    申请号：US17245299

    申请日：2021-04-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kohji KANAMORI ,  Hyun Mog PARK ,  Yong Seok KIM ,  Kyung Hwan LEE ,  Jun Hee LIM ,  Jee Hoon HAN

    IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

    摘要： A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190259439A1

    公开(公告)日：2019-08-22

    申请号：US16405219

    申请日：2019-05-07

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Chang Hoon JEON ,  Yong Seok KIM ,  Jun Hee LIM

    IPC分类号： G11C11/40 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/8238 ,  H01L27/092 ,  G11C16/04 ,  H01L21/8234

    摘要： A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240188294A1

    公开(公告)日：2024-06-06

    申请号：US18232948

    申请日：2023-08-11

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sam Ki KIM ,  Nam Bin KIM ,  Ji Woong KIM ,  Tae Hun KIM ,  Sae Rom LEE ,  Jun Hee LIM ,  Nag Yong CHOI ,  Sun Gyung HWANG

    IPC分类号： H10B43/27 ,  H10B43/40

    CPC分类号： H10B43/27 ,  H10B43/40

    摘要： A semiconductor memory device comprising a substrate including a cell array area and an extension area, a mold structure including, a plurality of gate electrodes sequentially stacked on the cell array area of the substrate and stacked in a stair shape on the extension area of the substrate, and a plurality of mold insulating films stacked alternately with the plurality of gate electrodes, a plurality of channel structures on the cell array area of the substrate, wherein each of the plurality of channel structures extends through the mold structure and intersects the plurality of gate electrodes, a plurality of cell contacts on the extension area of the substrate and respectively connected to the plurality of gate electrodes, a first interlayer insulating film on the mold structure so as to cover the plurality of channel structures and the plurality of cell contacts.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200381619A1

    公开(公告)日：2020-12-03

    申请号：US16998542

    申请日：2020-08-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kyung Hwan LEE ,  Chang Seok KANG ,  Yong Seok KIM ,  Kohji KANAMORI ,  Hui Jung KIM ,  Jun Hee LIM

    IPC分类号： H01L45/00 ,  H01L27/24 ,  H01L27/102

    摘要： A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190326511A1

    公开(公告)日：2019-10-24

    申请号：US16172830

    申请日：2018-10-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kyung Hwan LEE ,  Chang Seok KANG ,  Yong-Seok KIM ,  Kohji KANAMORI ,  Hui Jung KIM ,  Jun Hee LIM

    IPC分类号： H01L45/00 ,  H01L27/102 ,  H01L27/24

    摘要： A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180358079A1

    公开(公告)日：2018-12-13

    申请号：US15794628

    申请日：2017-10-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Chang Hoon JEON ,  Yong Seok KIM ,  Jun Hee LIM

    IPC分类号： G11C11/40

    CPC分类号： G11C11/40

    摘要： A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors, The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.