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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240155842A1

    公开(公告)日：2024-05-09

    申请号：US18510736

    申请日：2023-11-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo Joon RYU ,  Seo-Goo KANG ,  Hee Suk KIM ,  Jong Seon AHN ,  Kohji KANAMORI ,  Jee Hoon HAN

    IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

    Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.

    SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200350329A1

    公开(公告)日：2020-11-05

    申请号：US16690929

    申请日：2019-11-21

    Applicant: Samsung Electronics Co, Ltd.

    Inventor： Kohji KANAMORI ,  Seogoo KANG ,  Shinhwan KANG

    IPC: H01L27/11582 ,  H01L29/417

    Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

    VERTICAL MEMORY DEVICES
    5.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20200219893A1

    公开(公告)日：2020-07-09

    申请号：US16822596

    申请日：2020-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kohji KANAMORI

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06

    Abstract: A vertical memory device includes a gate electrode structure on a substrate, and a channel. The gate electrode structure includes gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrode structure in the vertical direction on the substrate. The channel includes a first portion having a slanted sidewall with respect to the upper surface of the substrate and a second portion contacting an upper surface of the first portion and having a slanted sidewall with respect to the upper surface of the substrate. A width of an upper surface of the second portion is less than a width of the upper surface of the first portion. An impurity region doped with carbon or p-type impurities is formed at an upper portion of the substrate. The channel contacts the impurity region.

    METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES
    6.
    发明申请
    METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20190013330A1

    公开(公告)日：2019-01-10

    申请号：US16117036

    申请日：2018-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji KANAMORI ,  Shin-Hwan KANG ,  Young-Woo PARK ,  Jung-Hoon PARK

    IPC: H01L27/11582 ,  H01L49/02 ,  H01L29/423

    CPC classification number: H01L27/11582 ,  H01L28/00 ,  H01L29/42344

    Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

    VERTICAL MEMORY DEVICES
    9.
    发明申请
    VERTICAL MEMORY DEVICES 有权

    公开(公告)号：US20220216234A1

    公开(公告)日：2022-07-07

    申请号：US17705513

    申请日：2022-03-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji KANAMORI ,  Shinhwan KANG

    IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

    Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE
    10.
    发明申请
    METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220139957A1

    公开(公告)日：2022-05-05

    申请号：US17579656

    申请日：2022-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je Suk MOON ,  Seo-Goo KANG ,  Young Hwan SON ,  Kohji KANAMORI ,  Jee Hoon HAN

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

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