公开(公告)号：US20210020509A1

公开(公告)日：2021-01-21

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20210111269A1

公开(公告)日：2021-04-15

申请号：US16794358

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan JUN ,  KANG-ILL SEO ,  Jeong Hyuk YIM

IPC: H01L29/66 ,  H01L29/78

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

公开(公告)号：US20210111257A1

公开(公告)日：2021-04-15

申请号：US16883308

申请日：2020-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan JUN ,  Jung Ho DO

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092

Abstract: Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.

公开(公告)号：US20200126858A1

公开(公告)日：2020-04-23

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan GWAK ,  Hwi Chan JUN ,  Heon Jong SHIN ,  So Ra YOU ,  Sang Hyun LEE ,  In Chan HWANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20190279930A1

公开(公告)日：2019-09-12

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUL KI HONG ,  Heon Jong SHIN ,  Hwi Chan JUN ,  Min Chan GWAK

IPC: H01L23/522 ,  H01L29/06 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/535 ,  H01L27/088 ,  H01L29/78 ,  H01L23/485 ,  H01L21/321 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US20230103070A1

公开(公告)日：2023-03-30

申请号：US18071168

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan JUN ,  Min Gyu KIM ,  Gil-Hwan SON

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/285

Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.

公开(公告)号：US20210242330A1

公开(公告)日：2021-08-05

申请号：US17026453

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan JUN ,  Min Gyu KIM ,  Gil-Hwan SON

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417

Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.