FREQUENCY MULTIPLIER EQUIPPED WITH ADAPTIVE VOLTAGE CONTROL BLOCK AND METHOD THEREFOR

    公开(公告)号:US20230378943A1

    公开(公告)日:2023-11-23

    申请号:US18156106

    申请日:2023-01-18

    CPC classification number: H03K5/00006 H03K17/56

    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system or a 6th-Generation (6G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system. A frequency multiplier of a wireless communication system is provided. The frequency multiplier includes an input circuit to which a local oscillator (LO) signal is input, a multiplier circuit having one end connected to the input circuit and another end connected to a lower terminal of a load circuit, a load circuit having an upper terminal connected to a voltage controller, and a voltage controller configured between the upper terminal of the load circuit and an input power source, wherein the voltage controller may be configured to drop a voltage between the input power source and the upper terminal of the load circuit and reinput a feedback voltage based on an upper terminal voltage of the load circuit to the voltage controller, and a method of multiplying a frequency using the same.

    LOW NOISE AMPLIFIER AND RECEIVER USING SAME IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20240333321A1

    公开(公告)日:2024-10-03

    申请号:US18615412

    申请日:2024-03-25

    CPC classification number: H04B1/0078 H04B1/04 H04B2001/0408

    Abstract: The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). A low noise amplifier (LNA) in a wireless communication system according to an embodiment of the disclosure includes a first transistor and a first feedback transformer in which a gate of the first transistor is connected to a primary coil of the first feedback transformer and a source of the first transistor is connected to a secondary coil of the first feedback transformer. The first feedback transformer is configured to implement positive feedback to maintain an in-phase signal at the gate of the first transistor and the source of the first transistor.

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