公开(公告)号：US11018045B2

公开(公告)日：2021-05-25

申请号：US15993752

申请日：2018-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Youn Seo ,  Byung Sun Park ,  Sung Jin Park ,  Ji Woon Im ,  Hyun Seok Lim ,  Byung Ho Chun ,  Yu Seon Kang ,  Hyuk Ho Kwon ,  Tae Yong Eom ,  Dae Hun Choi ,  Dong Hyeop Ha

IPC: H01L21/687 ,  C23C14/50 ,  C23C16/455 ,  H01J37/32 ,  C23C16/458

Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

公开(公告)号：US10971521B2

公开(公告)日：2021-04-06

申请号：US17034764

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Vit Yang ,  Yong Hoon Son ,  Moon Jong Kang ,  Hyuk Ho Kwon ,  Sung Soo Ahn ,  So Yoon Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.

公开(公告)号：US10804289B2

公开(公告)日：2020-10-13

申请号：US16237844

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Vit Yang ,  Yong Hoon Son ,  Moon Jong Kang ,  Hyuk Ho Kwon ,  Sung Soo Ahn ,  So Yoon Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/48

Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.

公开(公告)号：US11345998B2

公开(公告)日：2022-05-31

申请号：US15988067

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Sun Park ,  Ji Youn Seo ,  Ji Woon Im ,  Hyun Seok Lim ,  Byung Ho Chun ,  Yu Seon Kang ,  Hyuk Ho Kwon ,  Sung Jin Park ,  Tae Yong Eom ,  Dong Hyeop Ha

IPC: C23C16/455 ,  H01J37/32 ,  H01L21/02

Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.