公开(公告)号：US20230360689A1

公开(公告)日：2023-11-09

申请号：US18307098

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Young Park ,  Joo Hwan Kim ,  Jin Do Byun ,  Eun Seok Shin ,  Hyun Sub Rie ,  Hyun-Yoon Cho ,  Jung Hwan Choi

IPC: G11C11/4076 ,  H03K5/133 ,  H03L7/081 ,  H03K5/156

CPC classification number: G11C11/4076 ,  H03K5/133 ,  H03L7/0812 ,  H03K5/1565 ,  H01L25/18

Abstract: A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.