公开(公告)号：US12112827B2

公开(公告)日：2024-10-08

申请号：US17852664

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Hwan Kim ,  Jun Young Park ,  Jin Do Byun ,  Kwang Seob Shin ,  Eun Seok Shin ,  Hyun-Yoon Cho ,  Young Don Choi ,  Jung Hwan Choi

IPC: G11C7/10 ,  H03K19/00

CPC classification number: G11C7/1048 ,  G11C2207/2254 ,  H03K19/0005

Abstract: A method includes measuring a linearity of a first pull-up circuit, a second pull-up circuit, a third pull-up circuit, a first pull-down circuit, a second pull-down circuit and a third pull-down circuit using an initial pull-up code and an initial pull-down code, each of the first pull-up circuit, the second pull-up circuit and the third pull-up circuit having a respective resistance value determined based on a respective pull-up code, and each of the first pull-down circuit, the second pull-down circuit and the third pull-down circuit having a respective resistance value determined based on a respective pull-down code, and determining a calibration setting indicator based on the measurement result, the calibration setting indicator indicating a calibration method of a transmission driver including the first pull-up circuit, the second pull-up circuit, the third pull-up circuit, the first pull-down circuit, the second pull-down circuit and the third pull-down circuit.

公开(公告)号：US11461176B2

公开(公告)日：2022-10-04

申请号：US17398158

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young Park ,  Young-Hoon Son ,  Hyun-Yoon Cho ,  Young Don Choi ,  Jung Hwan Choi

IPC: G06F11/10 ,  H03M13/29 ,  G06F1/08

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

公开(公告)号：US20230360689A1

公开(公告)日：2023-11-09

申请号：US18307098

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Young Park ,  Joo Hwan Kim ,  Jin Do Byun ,  Eun Seok Shin ,  Hyun Sub Rie ,  Hyun-Yoon Cho ,  Jung Hwan Choi

IPC: G11C11/4076 ,  H03K5/133 ,  H03L7/081 ,  H03K5/156

CPC classification number: G11C11/4076 ,  H03K5/133 ,  H03L7/0812 ,  H03K5/1565 ,  H01L25/18

Abstract: A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.