公开(公告)号：US10236056B2

公开(公告)日：2019-03-19

申请号：US15428520

申请日：2017-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wook Seo ,  Jae-Seung Choi ,  Hyun-Su Choi

IPC: G11C7/22 ,  G11C11/419 ,  G11C5/14

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

公开(公告)号：US20170154673A1

公开(公告)日：2017-06-01

申请号：US15428520

申请日：2017-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wook SEO ,  Jae-Seung Choi ,  Hyun-Su Choi

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.