公开(公告)号：US20170154673A1

公开(公告)日：2017-06-01

申请号：US15428520

申请日：2017-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wook SEO ,  Jae-Seung Choi ,  Hyun-Su Choi

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/22 ,  G11C7/222

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

公开(公告)号：US20230337443A1

公开(公告)日：2023-10-19

申请号：US18126761

申请日：2023-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young TANG ,  Tae-Hyung KIM ,  Dae Young MOON ,  Sang-Yeop BAECK ,  Dong-Wook SEO

IPC: H10B80/00 ,  H10B10/00

CPC classification number: H10B80/00 ,  H10B10/18

Abstract: Provided are a three-dimensional (3D) semiconductor integrated circuit and a static random access memory (SRAM) device. The three-dimensional (3D) semiconductor integrated circuit includes: a first die including a power supply circuit a second die including an SRAM with a through-silicon-via (TSV) bundle region; a third die including a processor; and TSVs, each of which is provided on the TSV bundle region and extends from the TSV bundle region to the third die. The SRAM device includes: a bank array with banks, each of which includes sub-bit-cell arrays and a local peripheral circuit region arranged in a cross (+) shape between the sub-bit-cell arrays; and a global peripheral circuit region including a tail peripheral circuit region extending in a first direction and a head peripheral circuit region extending in a second direction, the tail peripheral circuit region and the head peripheral circuit region being arranged in a “T” shape.

公开(公告)号：US20230186982A1

公开(公告)日：2023-06-15

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung Kang ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H10B10/00 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H10B10/12 ,  H10B10/18 ,  H01L23/5286 ,  H01L27/092

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20210383861A1

公开(公告)日：2021-12-09

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20200005860A1

公开(公告)日：2020-01-02

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20170221554A1

公开(公告)日：2017-08-03

申请号：US15417807

申请日：2017-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Tae-Hyung KIM ,  Daeyoung MOON ,  Dong-Wook SEO ,  Inhak LEE ,  Hyunsu CHOI ,  Taejoong SONG ,  Jae-Seung CHOI ,  Jung-Myung KANG ,  Hoon KIM ,  Jisu YU ,  Sun-Yung JANG

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20160003901A1

公开(公告)日：2016-01-07

申请号：US14706224

申请日：2015-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Gyu PARK ,  Dong-Wook SEO ,  Chan-Ho LEE

IPC: G01R31/3177 ,  G01R31/317 ,  H03K3/037

CPC classification number: G01R31/318538 ,  G01R31/318555 ,  H03K3/0375

Abstract: A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop.

Abstract translation: 扫描链电路包括串联连接的第一到第N触发器，以响应于控制信号顺序传送数据，其中N是大于1的整数。在第一至第N触发器中，数据是 在第一方向从第一触发器转移到第N触发器。 控制信号以与从第N触发器到第一触发器的第一方向相反的第二方向施加到第一至第N触发器。