公开(公告)号：US20220262757A1

公开(公告)日：2022-08-18

申请号：US17736536

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho KO ,  Daehee LEE ,  Hyunchul JUNG

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US20210217720A1

公开(公告)日：2021-07-15

申请号：US16983296

申请日：2020-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho KO ,  Daehee LEE ,  Hyunchul JUNG

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US20230126003A1

公开(公告)日：2023-04-27

申请号：US17858536

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Jihye SHIM ,  Jung Hyun LEE ,  Hyunchul JUNG

IPC: H01L23/544 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

公开(公告)号：US20240429174A1

公开(公告)日：2024-12-26

申请号：US18750274

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Kwangbae KIM ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias; second vias; a bridge chip; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface; and a third via, some of the first vias are electrically connected to some of the bridge chip pads, some of the second vias are electrically connected to others of the bridge chip pads, and the passivation layer includes a same material as a material of the first dielectric film.

公开(公告)号：US20240128239A1

公开(公告)日：2024-04-18

申请号：US18471875

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Junyun KWEON ,  Byeongchan KIM ,  Jumyong PARK ,  Dongjoon OH ,  Hyunchul JUNG ,  Hyunsu HWANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor package includes a connection structure, a via protection layer on the connection structure, a first semiconductor chip on the via protection layer and including a first substrate having a first active face and a first inactive face opposite to each other a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure, and a second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip. The second semiconductor chip includes a second substrate having a second active face and a second inactive face opposite to each other. The package includes a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other, and a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer encloses the conductive post.

公开(公告)号：US20240088006A1

公开(公告)日：2024-03-14

申请号：US18317521

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Dongwoo KANG ,  Unbyoung KANG ,  Soohwan LEE ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/32235 ,  H01L2924/1434

Abstract: Provided is a semiconductor package including a substrate including a first surface and a second surface opposite to the first surface, a connecting circuit arranged on the first surface of the substrate, a through silicon via (TSV) structure penetrating the substrate, a first passivation layer arranged on the connecting circuit, a second passivation layer arranged on the second surface, a first bumping pad arranged inside the first passivation layer, and a second bumping pad arranged inside the second passivation layer, wherein the first bumping pad includes a first pad plug, and a first seed layer surrounding a lower surface and sidewalls of the first pad plug, wherein the second bumping pad includes a second pad plug, and a second seed layer surrounding an upper surface and sidewalls of the second pad plug, and wherein the first seed layer and the second seed layer include materials having different reactivities to water.

公开(公告)号：US20230082004A1

公开(公告)日：2023-03-16

申请号：US17874527

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun LEE ,  Junghoon KANG ,  Hyunchul JUNG

IPC: H01L21/56 ,  H01L23/498

Abstract: A method for manufacturing a semiconductor package includes forming a pad pattern including a metal film on a semiconductor chip; forming an insulating layer covering the pad pattern and including an organic insulating material; and forming an opening exposing a surface of the metal film of the pad pattern by performing laser processing on the insulating layer, wherein, in forming the opening, a region to be plastically deformed on the metal film by the laser processing is formed.

公开(公告)号：US20240421016A1

公开(公告)日：2024-12-19

申请号：US18667269

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Jing Cheng LIN ,  Jihwan SUH ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first molding layer, a dummy chip and a second molding layer. Each second semiconductor chip includes a semiconductor substrate comprising an active surface and an inactive surface opposite to the active surface. The first molding layer surrounds a portion of an upper surface of the first semiconductor chip and side surfaces of the second semiconductor chips and includes a trench that extends from an upper surface of the first molding layer into the first molding layer. The dummy chip is stacked on an uppermost second semiconductor chip of the second semiconductor chips. The second molding layer surrounds side surfaces of the dummy chip, and covers the first molding layer.