公开(公告)号：US20240178202A1

公开(公告)日：2024-05-30

申请号：US18356035

申请日：2023-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongchan KIM ,  Un-Byoung KANG ,  Jumyong PARK ,  Dongjoon OH ,  Jun Young OH ,  Jeongil LEE ,  Chungsun LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H10B80/00

Abstract: A semiconductor device includes: a semiconductor layer including a wire and an electrical element; and a plurality of metal pads on a surface of the semiconductor layer, wherein the plurality of metal pads includes a first metal pad and a second metal pad, wherein the second metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the first metal pad, and wherein the second metal pad is between a first region of the surface of the semiconductor layer where the first metal pad is and a second region of the surface of the semiconductor layer where a surface metal density is zero (0).

公开(公告)号：US20240312923A1

公开(公告)日：2024-09-19

申请号：US18677075

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20220037261A1

公开(公告)日：2022-02-03

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20230112006A1

公开(公告)日：2023-04-13

申请号：US17826521

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20230070532A1

公开(公告)日：2023-03-09

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20250015009A1

公开(公告)日：2025-01-09

申请号：US18885904

申请日：2024-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho KANG ,  Un-Byoung KANG ,  Byeongchan KIM ,  Junyoung PARK ,  Jongho LEE ,  Hyunsu HWANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20240128239A1

公开(公告)日：2024-04-18

申请号：US18471875

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Junyun KWEON ,  Byeongchan KIM ,  Jumyong PARK ,  Dongjoon OH ,  Hyunchul JUNG ,  Hyunsu HWANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor package includes a connection structure, a via protection layer on the connection structure, a first semiconductor chip on the via protection layer and including a first substrate having a first active face and a first inactive face opposite to each other a through-silicon via (TSV) configured to electrically connect the first semiconductor chip to the connection structure, and a second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip. The second semiconductor chip includes a second substrate having a second active face and a second inactive face opposite to each other. The package includes a conductive post configured to electrically connect the second semiconductor chip and the connection structure with each other, and a molding layer filling a space between an upper surface of the connection structure and the second semiconductor chip, and the molding layer encloses the conductive post.

公开(公告)号：US20220059466A1

公开(公告)日：2022-02-24

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.