公开(公告)号：US20230131062A1

公开(公告)日：2023-04-27

申请号：US17958811

申请日：2022-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungseuk KIM ,  Myunghoon CHOI

IPC: G06F3/06

Abstract: Provided are a storage device and an operating method thereof. The storage device includes: a memory storing parameter data that is used as an input in a neural network; and a storage controller configured to receive a request signal from a host, encode log data for contexts of a plurality of components in the neural network, based on the parameter data, and transmit the encoded log data to the host.

公开(公告)号：US20250068718A1

公开(公告)日：2025-02-27

申请号：US18615307

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungseuk KIM

IPC: G06F21/44 ,  G06F21/60 ,  G06F21/71

Abstract: A method of manufacturing a multi-chip includes generating a first authentication certificate in a first die using a private key of the first die, verifying the first authentication certificate in a second die using a public key of the first die, generating a second authentication certificate in the second die using a private key of the second die, and verifying the second authentication certificate using a public key of the second die in a third die.

公开(公告)号：US20230154525A1

公开(公告)日：2023-05-18

申请号：US17986556

申请日：2022-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungseuk KIM ,  Yongjun LEE

IPC: G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/52

Abstract: A storage device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a physical unclonable function (PUF) circuit configured to output PUF data based on a voltage difference between two memory cells from among the plurality of memory cells, the two memory cells being connected to a word line from among the plurality of word lines and two bit lines from among the plurality of bit lines, and to which a same data are programmed; and a memory controller configured to receive the PUF data from the PUF circuit, and program the PUF data or an inverted value of the PUF data to one of the two memory cells based on a value of the PUF data.

公开(公告)号：US20190050325A1

公开(公告)日：2019-02-14

申请号：US15796743

申请日：2017-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN ,  Hyungseuk KIM ,  Jinhyun KIM

IPC: G06F12/02 ,  G06F12/0862

Abstract: Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.