公开(公告)号：US20190146670A1

公开(公告)日：2019-05-16

申请号：US16231229

申请日：2018-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manu AWASTHI ,  Robert BRENNAN

IPC: G06F3/06

Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

公开(公告)号：US20160173101A1

公开(公告)日：2016-06-16

申请号：US14838347

申请日：2015-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu GAO ,  Hongzhong ZHENG ,  Krishna T. MALLADI ,  Robert BRENNAN

IPC: H03K19/177 ,  H01L25/00 ,  H01L25/18

CPC classification number: H03K19/1776 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17736 ,  H01L2924/00

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array.

Abstract translation: 根据一个一般方面，一种装置可以包括多个堆叠的集成电路管芯。 管芯可以包括被配置为以随机存取方式存储数据的存储单元管芯。 模具还可以包括查找表模具，其包括随机存取存储器阵列，其又包括可重新配置的查找表。 可重构查找表可以被配置为执行逻辑功能。 可配置查找表可以包括被配置为存储查询表以执行逻辑功能的多个随机存取存储器单元，以及配置成基于一组输入来激活一行或多行存储器单元的本地行解码器 信号。 存储在多个存储器单元中的查找表可以被配置为通过存储器写入操作来动态地改变到随机存取存储器阵列。

公开(公告)号：US20210117103A1

公开(公告)日：2021-04-22

申请号：US17133987

申请日：2020-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F15/78 ,  G06F13/42

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

公开(公告)号：US20190050325A1

公开(公告)日：2019-02-14

申请号：US15796743

申请日：2017-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN ,  Hyungseuk KIM ,  Jinhyun KIM

IPC: G06F12/02 ,  G06F12/0862

Abstract: Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.

公开(公告)号：US20160117225A1

公开(公告)日：2016-04-28

申请号：US14663220

申请日：2015-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang YU ,  Chang-Eun CHOI ,  Kyung Ho KIM ,  Walter JUN ,  Wonchuri ZOO ,  Robert BRENNAN

IPC: G06F11/14

CPC classification number: G06F11/1417 ,  G06F11/1004 ,  G06F11/1666 ,  G06F11/20

Abstract: Embodiments of the inventive concept include computer-implemented method for shadowing one or more boot images of a mobile device. The technique can include duplicating boot images to shadow partitions in a user area of a non-volatile memory device such as a flash memory. The technique can include detecting boot image corruption, and causing a mobile device to boot from the shadow partitions. The technique can include dynamically shadowing and releasing blocks used by the shadow partitions. The technique can include boot failure recovery and bad image preservation through firmware flash translation layer (FTL) logical to physical mapping updates. Boot image corruption failures can be recovered from and/or debugged using the shadow partitions.

Abstract translation: 本发明构思的实施例包括用于遮蔽移动设备的一个或多个引导映像的计算机实现的方法。 该技术可以包括将引导映像复制到诸如闪存之类的非易失性存储器设备的用户区域中的阴影分区。 该技术可以包括检测引导图像损坏，并使移动设备从影子分区引导。 该技术可以包括动态遮蔽和释放影子分区使用的块。 该技术可以通过固件闪存转换层（FTL）逻辑到物理映射更新来包括引导故障恢复和不良映像保存。 引导映像损坏故障可以使用影子分区恢复和/或调试。

公开(公告)号：US20160054933A1

公开(公告)日：2016-02-25

申请号：US14561204

申请日：2014-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siamack HAGHIGHI ,  Robert BRENNAN

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/06

CPC classification number: G06F3/0611 ,  G06F3/064 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0638 ,  G06F2212/205

Abstract: According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media.

Abstract translation: 根据一个一般方面，设备可以包括处理器，异构存储器系统和存储器互连。 处理器可以被配置为对存储在存储器系统中的数据执行数据访问。 异构存储器系统可以包括多种类型的存储介质。 每种类型的存储介质可以基于相应的存储器技术，并且可以与一个或多个性能特性相关联。 异构存储器系统可以包括易失性存储介质和非易失性存储介质。 至少部分地基于与存储介质的相应存储器技术相关联的一个或多个性能特征，存储器互连可被配置为将数据访问从处理器路由到至少一个存储介质。

公开(公告)号：US20200301582A1

公开(公告)日：2020-09-24

申请号：US16897264

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manu AWASTHI ,  Robert BRENNAN

IPC: G06F3/06

Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

公开(公告)号：US20190079677A1

公开(公告)日：2019-03-14

申请号：US15821686

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN

IPC: G06F3/06

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

公开(公告)号：US20180321876A1

公开(公告)日：2018-11-08

申请号：US15654493

申请日：2017-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chinnakrishnan BALLAPURAM ,  Ajay SUNDAR RAJ ,  Robert BRENNAN

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/065 ,  G06F3/0679 ,  H04L49/901 ,  H04L67/1097

Abstract: Improved latency and throughput associated with storage functionalities are provided by an Ethernet SSD (eSSD) system and corresponding method. The eSSD system includes at least one primary SSD, at least one secondary SSD, an Ethernet switch, and a storage-offload (SoE) controller. The SoE controller may operate in a replication mode and/or an erasure-coding mode. In either mode, the SoE controller receives a first write command sent from a remote device to at least one primary SSD. In the replication mode, the SoE controller sends a second write command to the at least one secondary SSD to replicate at the at least one secondary SSD data associated with the first write command. In the erasure-coding mode, the SoE determines erasure codes associated with the first write command and manages distribution of the write data and associated erasure codes.

公开(公告)号：US20180032403A1

公开(公告)日：2018-02-01

申请号：US15726375

申请日：2017-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang YU ,  Chang-Eun CHOI ,  Kyung Ho KIM ,  Walter JUN ,  Wonchuri ZOO ,  Robert BRENNAN

IPC: G06F11/14 ,  G06F11/16 ,  G06F11/20

CPC classification number: G06F11/1417 ,  G06F11/1004 ,  G06F11/1666 ,  G06F11/20

Abstract: Embodiments of the inventive concept include computer-implemented method for shadowing one or more boot images of a mobile device. The technique can include duplicating boot images to shadow partitions in a user area of a non-volatile memory device such as a flash memory. The technique can include detecting boot image corruption, and causing a mobile device to boot from the shadow partitions. The technique can include dynamically shadowing and releasing blocks used by the shadow partitions. The technique can include boot failure recovery and bad image preservation through firmware flash translation layer (FTL) logical to physical mapping updates. Boot image corruption failures can be recovered from and/or debugged using the shadow partitions.