公开(公告)号：US20230091724A1

公开(公告)日：2023-03-23

申请号：US17941570

申请日：2022-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun YOON ,  Jinwoo PARK

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/30

Abstract: Provided are a non-volatile memory device, a storage device including the same, and a method of performing a programming operation on the same. The method includes performing a program operation including applying a desired first program voltage to a selected word line of the memory device, the selected word line including a plurality of memory cells, performing a verification operation including sensing a first sensing value corresponding to an output of the selected word line based on a first verify voltage, and counting a number of on-cells of the selected word line based on the first sensing value to determine a first count value, determining whether a first program state of the selected word line has been verified based on the first count value and at least one reference value, and setting a second program voltage based on results of the determining whether the first program state has been verified.

公开(公告)号：US20230079939A1

公开(公告)日：2023-03-16

申请号：US18057328

申请日：2022-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejin KIM ,  Hyunjun YOON

IPC: G06F11/07 ,  G06F12/0882 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4074 ,  G06F13/16

Abstract: A non-volatile memory device, a method of operating the non-volatile memory device, and a memory system including the non-volatile memory device are provided. A non-volatile memory device includes a memory cell array including a plurality of memory cells configured to be each programmed to one state of a plurality of states, a page buffer circuit including a plurality of page buffers configured to each store received data as state data indicating a target state of a corresponding one of the plurality of memory cells, the page buffer circuit being configured to perform a state data reordering operation of changing a first state data order into a second state data order during performance of a program operation on selected memory cells of the plurality of memory cells, and a reordering control circuit configured to control the page buffer circuit to perform the state data reordering operation simultaneously with the program operation.