公开(公告)号：US20250119149A1

公开(公告)日：2025-04-10

申请号：US18897676

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Hyeseong Shin ,  Hyunwoo Ahn ,  Seonkyoo Lee ,  Hyunsung Lee ,  Daechul Jeong

IPC: H03L7/081 ,  G11C7/10 ,  H03L7/085 ,  H03L7/195

Abstract: A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).