公开(公告)号：US20240243059A1

公开(公告)日：2024-07-18

申请号：US18372881

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHO JANG ,  JUNSOO KIM ,  ILGWEON KIM ,  DONGSOO WOO ,  MOONYOUNG JEONG ,  JOON HAN

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H10B12/482

Abstract: A semiconductor device may include a substrate including an insulating substrate. A semiconductor layer is on the substrate. An active pattern is on the semiconductor layer. A bit line is disposed in the insulating substrate. The bit line extends along a first direction parallel to a bottom surface of the substrate. A buried node contact penetrates the semiconductor layer in a direction perpendicular to the bottom surface of the substrate. A word line penetrates the active pattern in a second direction that is parallel to the bottom surface of the substrate and crosses the first direction. The active pattern may be connected to the bit line through the buried node contact. A top surface of the buried node contact may be higher than a bottom surface of the active pattern.

公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.