公开(公告)号：US20210193661A1

公开(公告)日：2021-06-24

申请号：US17032040

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  SATORU YAMADA ,  SUNGWON YOO ,  JAEHO HONG

IPC: H01L27/108 ,  G11C7/18

Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

公开(公告)号：US20230115434A1

公开(公告)日：2023-04-13

申请号：US17868944

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  JONGMAN PARK ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/11507

Abstract: Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.

公开(公告)号：US20230397430A1

公开(公告)日：2023-12-07

申请号：US18303854

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  KEUNNAM KIM ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  KYUNGHWAN LEE

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.

公开(公告)号：US20220406797A1

公开(公告)日：2022-12-22

申请号：US17679255

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.

公开(公告)号：US20240259707A1

公开(公告)日：2024-08-01

申请号：US18399340

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHOON CHOI ,  SEUNGWON CHOI ,  HYUNCHEOL KIM ,  JONGSEONG CHOI

IPC: H04N25/61 ,  H04N23/71 ,  H04N23/72 ,  H04N23/75 ,  H04N23/76 ,  H04N25/51

CPC classification number: H04N25/61 ,  H04N23/71 ,  H04N23/72 ,  H04N23/75 ,  H04N23/76 ,  H04N25/51

Abstract: A lens shading correction circuit includes an elliptical gain generation circuit configured to extract a position of a pixel and generate an elliptical gain value using elliptical gain parameters and the extracted position and a multiplier configured to output an output value by multiplying the elliptical gain value by a weight for the pixel. The lens shading correction circuit corrects the lens shading based on the first output value and a gain increment value.

公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US20220367514A1

公开(公告)日：2022-11-17

申请号：US17671533

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  SUNGWON YOO ,  KYUNGHWAN LEE ,  JAEHO HONG

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor memory device may include a stack including word lines and interlayer insulating patterns alternatingly stacked on a substrate, the word lines being extended in a first direction parallel to a top surface of the substrate, semiconductor patterns crossing the word lines and having a long axis extended in a second direction parallel to the top surface of the substrate, data storage patterns respectively interposed between the semiconductor patterns and the word lines, the data storage patterns including a ferroelectric material, bit lines extended in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, each of the bit lines being in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction, and a source line in contact with second side surfaces of the semiconductor patterns.

公开(公告)号：US20220173139A1

公开(公告)日：2022-06-02

申请号：US17443791

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGDUCK LEE ,  SEUNGKI BAEK ,  KYUNGHO LEE ,  HYUNCHEOL KIM ,  DOOSIK SEOL ,  TAESUB JUNG ,  MASATO FUJITA

IPC: H01L27/146

Abstract: An image sensor includes: (1) a substrate having first and second surfaces opposing each other in a first direction and a plurality of unit pixels, (2) first and second photodiodes disposed in the substrate in each of the plurality of unit pixels and isolated from each other in a second direction perpendicular to the first direction, (3) a first device isolation film disposed between the plurality of unit pixels, and (4) a pixel internal isolation film disposed in at least one of the plurality of unit pixels. A second device isolation film overlaps at least one of the first and second photodiodes in the first direction. A pair of third device isolation films: (a) extend from the first device isolation film into the unit pixel in a third direction perpendicular to the first direction and the second direction and (b) oppose each other.