公开(公告)号：US20230223454A1

公开(公告)日：2023-07-13

申请号：US17898028

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUNJIN KIM ,  KI HO BAE ,  BOUN YOON ,  ILYOUNG YOON

IPC: H01L29/423 ,  H01L29/417

CPC classification number: H01L29/4238 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/41766

Abstract: A semiconductor device may include a substrate including a first cell region, a second cell region, and a dummy region between the first and second cell regions, and conductive patterns included in the first cell region, the second cell region, and the dummy region. A first pattern density, which is defined as a density of the conductive patterns of the first cell region, may be different from a second pattern density, which is defined as a density of the conductive patterns of the second cell region. A third pattern density, which is defined as a density of the conductive patterns of the dummy region, gradually changes in a region between the first cell region and the second cell region. A top surface of the substrate may be inclined at an angle, in the dummy region.

公开(公告)号：US20240251544A1

公开(公告)日：2024-07-25

申请号：US18474394

申请日：2023-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN SHIN ,  SANGJUN PARK ,  SUNGJOO AN ,  KIJONG PARK ,  ILYOUNG YOON

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a bit line positioned on the substrate and extending in a first direction; a channel accommodating insulating layer positioned on the substrate, and defining a channel trench exposing the bit line and extending in a second direction crossing the first direction; a channel layer extending along a bottom surface and a side surface of the channel trench and contacting the bit line; a word line positioned in the channel trench and extending in the second direction; a gate insulating layer positioned between the channel layer and the word line; and a capacitor structure positioned on the channel layer and electrically connected to the channel layer, in which the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer.

公开(公告)号：US20240227112A1

公开(公告)日：2024-07-11

申请号：US18225909

申请日：2023-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGJUN LEE ,  Jinoh Im ,  ILYOUNG YOON

IPC: B24B37/013

CPC classification number: B24B37/013

Abstract: A chemical mechanical polishing apparatus according to an example embodiment includes a polishing platen; a polishing pad which is located on the polishing platen and includes a polishing surface; a slurry supplier configured to supply a slurry to the polishing pad; a polishing head which is located above the polishing pad and configured to mount a wafer thereon; and an additional CMP process condition generator which generates an additional chemical mechanical polishing (CMP) process condition according to a type of residue when there is a residue on a wafer after a CMP process is performed on the wafer.