公开(公告)号：US20210020578A1

公开(公告)日：2021-01-21

申请号：US17036702

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun JEE ,  Il Hwan KIM ,  Un Byoung KANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US20200066545A1

公开(公告)日：2020-02-27

申请号：US16293697

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il Hwan KIM ,  Un Byoung KANG ,  Chung Sun LEE

IPC: H01L21/48 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

公开(公告)号：US20240404863A1

公开(公告)日：2024-12-05

申请号：US18407872

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Yong YU ,  Woo Jeong SHIN ,  Il Hwan KIM ,  Chang Min PARK ,  Hee Sun JUN

IPC: H01L21/683 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device may include forming a first substrate including a first surface and a second surface, which may be opposite each other, forming a first semiconductor element on the first surface, adhering the first substrate onto a second substrate so that an upper surface of the second substrate faces the first surface of the first substrate, removing an edge region of the first substrate, forming a passivation layer surrounding first sides of the first substrate, and forming a second semiconductor element on the second surface of the first substrate. The passivation layer may not be formed on the second surface of the first substrate.