公开(公告)号：US20200098719A1

公开(公告)日：2020-03-26

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick PARK ,  Un Byoung KANG ,  Tae Hong MIN ,  Teak Hoon LEE ,  Ji Hwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

公开(公告)号：US20240379626A1

公开(公告)日：2024-11-14

申请号：US18780917

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun SHIN ,  Un Byoung KANG ,  Yeong Kwon KO ,  Jong Ho LEE ,  Teak Hoon LEE ,  Jun Yeong HEO

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

公开(公告)号：US20210020578A1

公开(公告)日：2021-01-21

申请号：US17036702

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun JEE ,  Il Hwan KIM ,  Un Byoung KANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11 ,  H01L25/07

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

公开(公告)号：US20200066545A1

公开(公告)日：2020-02-27

申请号：US16293697

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il Hwan KIM ,  Un Byoung KANG ,  Chung Sun LEE

IPC: H01L21/48 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of trenches at a first surface of a silicon substrate, forming a conductive pad inside each of the plurality of trenches, forming a redistribution layer on the first surface of the silicon substrate, forming an external connection terminal on a first surface of the redistribution layer, removing the silicon substrate to expose each conductive pad, mounting a semiconductor chip to be connected to the conductive pads, and forming an encapsulant to cover at least one surface of the semiconductor chip.

公开(公告)号：US20220293565A1

公开(公告)日：2022-09-15

申请号：US17531115

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun SHIN ,  Un Byoung KANG ,  Yeong Kwon KO ,  Jong Ho LEE ,  Teak Hoon LEE ,  Jun Yeong HEO

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: There is provided a semiconductor device comprising a first semiconductor chip which includes a first chip substrate, and a first through via penetrating the first chip substrate, a second semiconductor chip disposed on the first semiconductor chip, and includes a second chip substrate, and a second through via penetrating the second chip substrate, and a connecting terminal disposed between the first semiconductor chip and the second semiconductor chip to electrically connect the first through via and the second through via. The semiconductor device further comprising an inter-chip molding material which includes a filling portion that fills between the first semiconductor chip and the second semiconductor chip and encloses the connecting terminal, an extension portion that extends along at least a part of a side surface of the second semiconductor chip, and a protruding portion protruding from the extension portion.

公开(公告)号：US20200006242A1

公开(公告)日：2020-01-02

申请号：US16201380

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Kun JEE ,  II Hwan KIM ,  Un Byoung KANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.