公开(公告)号：US20240063155A1

公开(公告)日：2024-02-22

申请号：US18296500

申请日：2023-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  Joonghyun Baek ,  Hyungu Kang ,  Taeyoung Kim ,  Jaekyu Sung ,  Cheolwoo Lee

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/06 ,  H10B80/00 ,  H01L2224/0401 ,  H01L2224/06519 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A stack semiconductor package including a base chip, at least two semiconductor chips stacked on the base chip, and a sealing material sealing the at least two semiconductor chips on the base chip may be provided. The at least two semiconductor chips may include an uppermost semiconductor chip and at least one under the uppermost semiconductor chip, the first semiconductor chip includes through electrodes at a central portion thereof along a first direction, the through electrodes arranged along a second direction perpendicular to the first direction, upper dummy pads on outer portions of a back side of the first semiconductor chip, the outer portions being a non-active surface of the first semiconductor chip and being at both sides of the central portion in the first direction, and a dummy pattern connecting the upper dummy pads with each other on the back side.

公开(公告)号：US12237304B2

公开(公告)日：2025-02-25

申请号：US17665810

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong Park ,  Do-Hyun Kim ,  Jaekyu Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

公开(公告)号：US11791303B2

公开(公告)日：2023-10-17

申请号：US18099092

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungu Kang ,  Jaekyu Sung

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/06102 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48148 ,  H01L2224/48158 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/182

Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

公开(公告)号：US11569193B2

公开(公告)日：2023-01-31

申请号：US17223614

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungu Kang ,  Jaekyu Sung

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.