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公开(公告)号:US09653382B2
公开(公告)日:2017-05-16
申请号:US14864810
申请日:2015-09-24
发明人: Jui-Ying Lin , Yen-Hsiang Fang , Chia-Hsin Chao , Yao-Jun Tsai , Yi-Chen Lin
IPC分类号: H01S5/024 , H01S5/026 , H01S5/34 , H01L23/48 , H01L21/306 , H01L27/02 , H01L33/20 , H01L33/62 , H01L21/768 , H01L23/00 , H01S5/02 , G02B6/12 , G02B6/34 , H01L29/861 , H01L23/60 , H01L23/13 , H01L23/14 , H01L23/498 , H01L21/48 , H01L25/16
CPC分类号: H01L23/481 , G02B6/12 , G02B6/34 , G02B2006/12061 , H01L21/30604 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/80 , H01L25/167 , H01L27/0255 , H01L29/861 , H01L33/20 , H01L33/62 , H01L2224/04 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06102 , H01L2224/08148 , H01L2224/08238 , H01L2224/16148 , H01L2224/16238 , H01L2224/29294 , H01L2224/32148 , H01L2224/32238 , H01L2224/48091 , H01L2224/48105 , H01L2224/48148 , H01L2224/48229 , H01L2224/73265 , H01L2224/80801 , H01L2224/80805 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83805 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01322 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1434 , H01L2933/0066 , H01S5/0208 , H01S5/02469 , H01S5/026 , H01S5/34 , H01L2924/00 , H01L2224/80 , H01L2924/00012 , H01L2224/45099
摘要: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.
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公开(公告)号:US09582704B2
公开(公告)日:2017-02-28
申请号:US14911573
申请日:2014-08-22
申请人: Fingerprint Cards AB
发明人: Pontus Jägemalm , Karl Lundahl , Mats Slottner , Hans Thörnblom , Ojie Julian
CPC分类号: G06K9/0002 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/48 , H01L24/49 , H01L2224/033 , H01L2224/0345 , H01L2224/03462 , H01L2224/035 , H01L2224/04042 , H01L2224/05022 , H01L2224/05624 , H01L2224/05647 , H01L2224/06179 , H01L2224/48091 , H01L2224/48148 , H01L2224/48465 , H01L2224/48471 , H01L2224/49175 , H01L2224/85186 , H01L2924/00014 , H01L2924/10155 , H01L2924/10157 , H01L2924/181 , H01L2224/45099 , H01L2924/00 , H01L2924/00012 , H01L2224/4554
摘要: A fingerprint sensing device comprising sensing circuitry comprising a plurality of sensing elements, each sensing element comprising a sensing structure arranged in a sensing plane and facing a surface of the capacitive fingerprint sensing device, each of the sensing elements being configured to provide a signal indicative of an electromagnetic coupling between the sensing structure and a finger placed on the surface of the fingerprint sensing device; and a plurality of connection pads electrically connected to the sensing circuitry for providing an electrical connection between the sensing circuitry and readout circuitry, wherein each of the connection pads is separately recessed in relation to the sensing plane such that each connection pad has a floor in a floor plane, and wherein each connection pad is separated from an adjacent connection pad through a portion of the sensing device being elevated in relation to the floor plane.
摘要翻译: 一种指纹感测装置,包括感测电路,其包括多个感测元件,每个感测元件包括布置在感测平面中并面向电容式指纹感测装置的表面的感测结构,每个感测元件被配置为提供指示 感测结构和放置在指纹感测装置的表面上的手指之间的电磁耦合; 以及电连接到感测电路的多个连接焊盘,用于在感测电路和读出电路之间提供电连接,其中每个连接焊盘相对于感测平面分别凹陷,使得每个连接焊盘具有位于 底板平面,并且其中每个连接垫通过相对于底板平面升高的感测装置的一部分与相邻的连接垫分离。
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公开(公告)号:US09054105B2
公开(公告)日:2015-06-09
申请号:US13934485
申请日:2013-07-03
发明人: Keun-Ho Choi
IPC分类号: H01L23/52 , H01L23/522 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/065
CPC分类号: H01L23/5221 , H01L23/3128 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05553 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48148 , H01L2224/48227 , H01L2224/49113 , H01L2224/4941 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2224/48145 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/05599
摘要: A semiconductor package includes a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire having a reverse loop configuration.
摘要翻译: 半导体封装包括安装板,其包括接合焊盘,顺序地堆叠在安装板上的第一和第二半导体芯片,将焊盘的第一区域连接到第一半导体芯片的芯片焊盘的第一引线和连接 所述接合焊盘的第一区域到所述第二半导体芯片的芯片焊盘,所述第二引线具有反向回路配置。
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公开(公告)号:US20180114776A1
公开(公告)日:2018-04-26
申请号:US15623891
申请日:2017-06-15
申请人: Won-Gil HAN , Byong-Joo KIM , Yong-Je LEE , Jae-Heung LEE , Seung-Weon HA
发明人: Won-Gil HAN , Byong-Joo KIM , Yong-Je LEE , Jae-Heung LEE , Seung-Weon HA
IPC分类号: H01L25/065
CPC分类号: H01L25/0657 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L25/0652 , H01L25/50 , H01L2224/03334 , H01L2224/04042 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48095 , H01L2224/48106 , H01L2224/48145 , H01L2224/48148 , H01L2224/48149 , H01L2224/48151 , H01L2224/48227 , H01L2224/48482 , H01L2224/49176 , H01L2224/73215 , H01L2224/73265 , H01L2224/85181 , H01L2224/85186 , H01L2224/92247 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06568 , H01L2924/15311 , H01L2924/00012 , H01L2224/85
摘要: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.
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公开(公告)号:US09252079B2
公开(公告)日:2016-02-02
申请号:US14472391
申请日:2014-08-29
发明人: Yao-Jun Tsai , Chen-Peng Hsu , Shih-Yi Wen , Chi-Chin Yang , Hung-Lieh Hu
IPC分类号: H01L21/00 , H01L29/00 , H01L23/48 , H01L21/306 , H01L27/02 , H01L33/20 , H01L33/62 , H01L21/768 , H01L23/00 , H01S5/02 , H01S5/024 , H01S5/026 , H01S5/34 , G02B6/12 , G02B6/34 , H01L29/861 , H01L23/60 , H01L25/16
CPC分类号: H01L23/481 , G02B6/12 , G02B6/34 , G02B2006/12061 , H01L21/30604 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/80 , H01L25/167 , H01L27/0255 , H01L29/861 , H01L33/20 , H01L33/62 , H01L2224/04 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06102 , H01L2224/08148 , H01L2224/08238 , H01L2224/16148 , H01L2224/16238 , H01L2224/29294 , H01L2224/32148 , H01L2224/32238 , H01L2224/48091 , H01L2224/48105 , H01L2224/48148 , H01L2224/48229 , H01L2224/73265 , H01L2224/80801 , H01L2224/80805 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83805 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01322 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1434 , H01L2933/0066 , H01S5/0208 , H01S5/02469 , H01S5/026 , H01S5/34 , H01L2924/00 , H01L2224/80 , H01L2924/00012 , H01L2224/45099
摘要: Provided is a substrate, including a substrate material, two conductive structures, and at least one diode. The two conductive structures extend from a first surface of the substrate material to a second surface of the substrate material via two through holes penetrating through the substrate material. The at least one diode is embedded in the substrate material at a sidewall of one of the through holes.
摘要翻译: 提供了包括基板材料,两个导电结构和至少一个二极管的基板。 两个导电结构通过穿过衬底材料的两个通孔从衬底材料的第一表面延伸到衬底材料的第二表面。 所述至少一个二极管被嵌入在所述通孔之一的侧壁处的所述衬底材料中。
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公开(公告)号:US20140008796A1
公开(公告)日:2014-01-09
申请号:US13934485
申请日:2013-07-03
申请人: Keun-Ho CHOI
发明人: Keun-Ho CHOI
IPC分类号: H01L23/522
CPC分类号: H01L23/5221 , H01L23/3128 , H01L23/49811 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05553 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48148 , H01L2224/48227 , H01L2224/49113 , H01L2224/4941 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2224/48145 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/05599
摘要: A semiconductor package includes a mounting board including a bonding pad, first and second semiconductor chips sequentially stacked on the mounting board, a first wire connecting a first region of the bonding pad to a chip pad of the first semiconductor chip, and a second wire connecting the first region of the bonding pad to a chip pad of the second semiconductor chip, the second wire having a reverse loop configuration.
摘要翻译: 半导体封装包括安装板,其包括接合焊盘,顺序地堆叠在安装板上的第一和第二半导体芯片,将焊盘的第一区域连接到第一半导体芯片的芯片焊盘的第一引线和连接 所述接合焊盘的第一区域到所述第二半导体芯片的芯片焊盘,所述第二引线具有反向回路配置。
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公开(公告)号:US20130285248A1
公开(公告)日:2013-10-31
申请号:US13836807
申请日:2013-03-15
发明人: Hung-Lin Yin , Jerwei Hsieh , Li-Yuan Lin
IPC分类号: H01L23/498 , H01L21/762
CPC分类号: H01L23/49866 , B81C1/00269 , B81C2203/019 , H01L21/50 , H01L21/76251 , H01L23/10 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L25/0657 , H01L25/50 , H01L2224/0347 , H01L2224/03614 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05655 , H01L2224/05669 , H01L2224/1145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11614 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/16148 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/2745 , H01L2224/27462 , H01L2224/2747 , H01L2224/27614 , H01L2224/29011 , H01L2224/2908 , H01L2224/29082 , H01L2224/29084 , H01L2224/29111 , H01L2224/29139 , H01L2224/32146 , H01L2224/32148 , H01L2224/32235 , H01L2224/32238 , H01L2224/32503 , H01L2224/32507 , H01L2224/48091 , H01L2224/48148 , H01L2224/48228 , H01L2224/48463 , H01L2224/73103 , H01L2224/73203 , H01L2224/73215 , H01L2224/81011 , H01L2224/81013 , H01L2224/81022 , H01L2224/81121 , H01L2224/81193 , H01L2224/81203 , H01L2224/81825 , H01L2224/81948 , H01L2224/83011 , H01L2224/83013 , H01L2224/83022 , H01L2224/83121 , H01L2224/83193 , H01L2224/83203 , H01L2224/83805 , H01L2224/83825 , H01L2224/83948 , H01L2224/9202 , H01L2224/92147 , H01L2224/95 , H01L2924/00014 , H01L2924/01322 , H01L2924/1461 , H01L2924/15787 , H01L2924/16235 , H01L2924/351 , H01L2924/00015 , H01L2224/83 , H01L2224/85 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A substrate bonding method comprises the following steps. Firstly, a first substrate and a second substrate are provided, wherein a surface of the first substrate is covered by a first Ag layer and a surface of the second substrate is covered by a second Ag layer and a metallic layer from bottom to top, wherein the metallic layer comprises a first Sn layer. Secondly, a bonding process is performed by aligning the first and second substrates followed by bringing the metallic layer into contact with the first Ag layer followed by applying a load while heating to a predetermined temperature in order to form Ag3Sn intermetallic compounds. Finally, cool down and remove the load to complete the bonding process.
摘要翻译: 基板接合方法包括以下步骤。 首先,提供第一基板和第二基板,其中第一基板的表面被第一Ag层覆盖,并且第二基板的表面被从第二Ag层和从底部到顶部的金属层覆盖,其中 金属层包括第一Sn层。 其次,通过使第一和第二基板对准,然后使金属层与第一Ag层接触,然后在加热至预定温度的同时施加负载以形成Ag 3 Sn金属间化合物,进行接合工艺。 最后,冷却并清除负载以完成粘合过程。
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公开(公告)号:US09208827B2
公开(公告)日:2015-12-08
申请号:US14526802
申请日:2014-10-29
申请人: SK hynix Inc.
发明人: Ki Yong Lee , Jong Hyun Kim , Sang Hwan Kim
IPC分类号: H01L23/48 , H01L23/52 , H01L29/40 , H01L23/02 , G11C5/02 , H01L25/065 , H01L23/00 , G11C7/14 , H01L23/525 , G11C7/10 , G11C5/14 , G11C29/12
CPC分类号: G11C5/025 , G11C5/14 , G11C7/1057 , G11C7/1063 , G11C7/109 , G11C7/14 , G11C7/20 , G11C29/1201 , G11C2207/105 , H01L23/5256 , H01L24/09 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/0901 , H01L2224/0903 , H01L2224/09179 , H01L2224/09515 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48106 , H01L2224/48147 , H01L2224/48148 , H01L2224/48227 , H01L2224/49176 , H01L2224/49177 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/1207 , H01L2924/13091 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.
摘要翻译: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底,堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元,并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元,设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。
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公开(公告)号:US09171779B2
公开(公告)日:2015-10-27
申请号:US14472400
申请日:2014-08-29
发明人: Jui-Ying Lin , Yen-Hsiang Fang , Chia-Hsin Chao , Yao-Jun Tsai , Yi-Chen Lin
IPC分类号: H01S5/024 , H01L23/48 , H01L21/306 , H01L27/02 , H01L33/20 , H01L33/62 , H01L21/768 , H01L23/00 , H01S5/02 , H01S5/026 , H01S5/34 , G02B6/12 , G02B6/34 , H01L29/861
CPC分类号: H01L23/481 , G02B6/12 , G02B6/34 , G02B2006/12061 , H01L21/30604 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/80 , H01L25/167 , H01L27/0255 , H01L29/861 , H01L33/20 , H01L33/62 , H01L2224/04 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/06102 , H01L2224/08148 , H01L2224/08238 , H01L2224/16148 , H01L2224/16238 , H01L2224/29294 , H01L2224/32148 , H01L2224/32238 , H01L2224/48091 , H01L2224/48105 , H01L2224/48148 , H01L2224/48229 , H01L2224/73265 , H01L2224/80801 , H01L2224/80805 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83805 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01322 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1434 , H01L2933/0066 , H01S5/0208 , H01S5/02469 , H01S5/026 , H01S5/34 , H01L2924/00 , H01L2224/80 , H01L2924/00012 , H01L2224/45099
摘要: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.
摘要翻译: 提供半导体激光器结构。 半导体激光器包括中心热分流器,环形硅波导,连续热分流器,粘合剂层和激光元件。 中心热分流器位于具有围绕中心热分流的掩埋氧化物层的SOI衬底上。 环形硅波导位于掩埋氧化层上并围绕中心热分流。 环形硅波导包括p型材料部分的P-N结,n型材料部分和其间的耗尽区域。 连续的热分流器覆盖一部分掩埋的氧化物层并且环绕着环形硅波导。 粘合剂层覆盖环形硅波导和掩埋氧化物层。 激光元件覆盖中心热分流器,粘合剂层和相邻热分流器。
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公开(公告)号:US20150302900A1
公开(公告)日:2015-10-22
申请号:US14526802
申请日:2014-10-29
申请人: SK hynix Inc.
发明人: Ki Yong LEE , Jong Hyun KIM , Sang Hwan KIM
IPC分类号: G11C5/02 , H01L23/00 , G11C29/12 , H01L23/525 , G11C7/10 , G11C5/14 , H01L25/065 , G11C7/14
CPC分类号: G11C5/025 , G11C5/14 , G11C7/1057 , G11C7/1063 , G11C7/109 , G11C7/14 , G11C7/20 , G11C29/1201 , G11C2207/105 , H01L23/5256 , H01L24/09 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/0901 , H01L2224/0903 , H01L2224/09179 , H01L2224/09515 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48106 , H01L2224/48147 , H01L2224/48148 , H01L2224/48227 , H01L2224/49176 , H01L2224/49177 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/1207 , H01L2924/13091 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.
摘要翻译: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底,堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元,并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元,设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。
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