公开(公告)号：US20230410891A1

公开(公告)日：2023-12-21

申请号：US18458743

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20170200507A1

公开(公告)日：2017-07-13

申请号：US15391883

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Jae JEONG ,  Je Min RYU

IPC: G11C17/18 ,  G11C29/04 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C17/16 ,  G11C29/04 ,  G11C29/78 ,  G11C29/812 ,  G11C2207/105

Abstract: A memory system includes a plurality of first signal lines to connect a plurality of memory devices to one another. The memory devices include a first memory device and at least one second memory device. The first memory device has at least one fuse cell and outputs fuse information set based on whether each of the at least one fuse cell is programmed. The at least one second memory device receives the fuse information and selectively activates the first signal lines based on the fuse information. The at least one second memory device simultaneously operates based on the fuse information received from the first memory device.

公开(公告)号：US20220310154A1

公开(公告)日：2022-09-29

申请号：US17685067

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20210104498A1

公开(公告)日：2021-04-08

申请号：US17124762

申请日：2020-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SeungHan WOO ,  Je Min RYU ,  Reum OH ,  Moonhee OH ,  BumSuk LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  G01R31/28

Abstract: A semiconductor die may include a first delay circuit formed on a substrate and configured to delay a test signal, the first delay circuit including first delay stages connected in series, a second delay circuit formed on the substrate and configured to delay the test signal, the second delay circuit including second delay stages connected in series, at least one through silicon via connected to at least one output terminal of output terminals of the first delay stages, the at least one through silicon via penetrating through the substrate, and a load determinator configured to compare a first delay signal output from one of the first delay stages with a second delay signal output from one of the second delay stages and determine a load of the at least one through silicon via.