公开(公告)号：US20230195327A1

公开(公告)日：2023-06-22

申请号：US18050585

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jehyun Park ,  Kwanho Kim

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0673 ,  G06F3/0653

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.

公开(公告)号：US12079488B2

公开(公告)日：2024-09-03

申请号：US18050585

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jehyun Park ,  Kwanho Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C29/42

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/1048 ,  G11C29/42

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a memory cell array including a plurality of memory cells configured to store data, a refresh controller configured to control a refresh operation with respect to the plurality of memory cells, and an error monitoring circuit configured to generate error information by monitoring an error in the data stored in the memory cell array based on refresh sensing data provided from the memory cell array during the refresh operation. The memory controller includes an error correction code (ECC) circuit and is further configured to correct the error in the data stored in the memory cell array using the ECC circuit based on the error information.