公开(公告)号：US11923035B2

公开(公告)日：2024-03-05

申请号：US17668760

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

公开(公告)号：US20240185896A1

公开(公告)日：2024-06-06

申请号：US18441089

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

公开(公告)号：US20220366944A1

公开(公告)日：2022-11-17

申请号：US17668760

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.