公开(公告)号：US11437320B2

公开(公告)日：2022-09-06

申请号：US16835557

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Youn ,  Chan Ho Lee ,  Uk Rae Cho ,  Woo jin Jung ,  Kyu Won Choi

IPC: G11C7/18 ,  H01L23/528 ,  H01L27/105 ,  H01L29/06 ,  G11C8/14 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.

公开(公告)号：US20210028109A1

公开(公告)日：2021-01-28

申请号：US16835557

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Youn ,  Chan Ho Lee ,  Uk Rae Cho ,  Woo jin Jung ,  Kyu Won Choi

IPC: H01L23/528 ,  H01L27/105 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor device includes a substrate including a first cell region, a second cell region adjacent to the first cell region in a first direction, and a comparison region adjacent the first and second cell regions in a second direction, a bit line in a first metal level on the substrate and extending in the first direction, and a first ground rail in a second metal level different from the first metal level. The first ground rail comprises a first sub-ground rail extending in the second direction on the first cell region, a second sub-ground rail extending in the second direction on the second cell region, a third sub-ground rail connecting the first sub-ground rail to the second sub-ground rail on the first and second cell regions, and a fourth sub-ground rail that branches off from the third sub-ground rail and extends in the second direction.

公开(公告)号：US12080348B2

公开(公告)日：2024-09-03

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US11923035B2

公开(公告)日：2024-03-05

申请号：US17668760

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

公开(公告)号：US20230178151A1

公开(公告)日：2023-06-08

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US20250095735A1

公开(公告)日：2025-03-20

申请号：US18664549

申请日：2024-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinmyeong Hong ,  Suk Youn ,  Taehyung Kim ,  Hoyoung Tang

IPC: G11C15/04

Abstract: An example integrated circuit includes a ternary content-addressable memory (TCAM) cell on a front side of a substrate, a backside via extending through the substrate in a vertical direction with respect to the substrate, a backside wiring layer on a back side of the substrate, and a frontside wiring layer above the TCAM cell in the vertical direction. The TCAM cell includes a first cell storing a first value, a second cell storing a second value, and a comparison circuit connected with the first and second cells. The backside wiring layer includes at least one backside power rail configured to transmit a supply voltage to the TCAM cell through the backside via. The frontside wiring layer includes a bit line connected with the first and second cells, a complementary bit line connected with the first and second cells, and a match line connected with the comparison circuit.

公开(公告)号：US20240185896A1

公开(公告)日：2024-06-06

申请号：US18441089

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

公开(公告)号：US20220366944A1

公开(公告)日：2022-11-17

申请号：US17668760

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Ho Lee ,  Tae Min Choi ,  Jeong Kyun Kim ,  Hyeong Cheol Kim ,  Suk Youn ,  Ju Chang Lee ,  Kyu Won Choi

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.