公开(公告)号：US12062626B2

公开(公告)日：2024-08-13

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20220059472A1

公开(公告)日：2022-02-24

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20230275037A1

公开(公告)日：2023-08-31

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US12015005B2

公开(公告)日：2024-06-18

申请号：US17537994

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom Ko ,  Wooju Kim ,  Heejae Nam ,  Jungseok Ryu ,  Haemin Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/10156

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20240178000A1

公开(公告)日：2024-05-30

申请号：US18519501

申请日：2023-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jesung Kim ,  Haemin Park ,  Heejae Nam ,  Junggeun Shin ,  Junho Yoon ,  Jungho Choi

IPC: H01L21/304 ,  B23K26/53 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/3043 ,  B23K26/53 ,  H01L21/6836 ,  H01L21/78 ,  B23K2101/40 ,  H01L2221/68327

Abstract: A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.

公开(公告)号：US11676914B2

公开(公告)日：2023-06-13

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.