公开(公告)号：US10153277B2

公开(公告)日：2018-12-11

申请号：US15390361

申请日：2016-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Gi-gwan Park ,  Ji-myoung Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8258

Abstract: An integrated circuit device includes: a pair of width-setting patterns over a substrate, the pair of width-setting patterns defining a width of a gate structure space in a first direction and extending in a second direction intersecting with the first direction. A gate electrode layer is provided that extends in the gate structure space along the second direction. A gate insulating layer is provided in the gate structure space and between the substrate and the gate electrode layer. An insulating spacer is provides on the pair of width-setting patterns, the insulating spacer covering both sidewalls of the gate electrode layer, wherein the pair of width-setting patterns have a carbon content that is greater than a carbon content of the insulating spacer.

公开(公告)号：US09318477B2

公开(公告)日：2016-04-19

申请号：US14493526

申请日：2014-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-myoung Lee ,  Young-soo Song ,  Bo-young Lee ,  Jun-min Lee

IPC: H01L27/02 ,  H01L21/8238 ,  G11C7/14

CPC classification number: H01L27/0207 ,  G11C7/14 ,  H01L21/823821 ,  H01L21/823828

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.

Abstract translation: 公开了一种半导体器件。 半导体器件包括在第一方向上彼此平行并沿与第一方向正交的第二方向延伸的多个虚拟栅极线; 所述多个虚拟栅极线之间的多个第一虚拟填充图案，所述第一虚拟填充图案在所述第一方向上彼此平行，并且沿所述第二方向彼此分离布置; 多个第一虚拟填充图案中的多个第一虚拟通孔; 以及连接到所述多个第一虚拟通孔的多个第一虚拟布线，所述第一虚拟通路沿所述第二方向延伸，并且沿所述第一方向彼此平行。

公开(公告)号：US20150091188A1

公开(公告)日：2015-04-02

申请号：US14493526

申请日：2014-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-myoung Lee ,  Young-soo Song ,  Bo-young Lee ,  Jun-min Lee

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L27/0207 ,  G11C7/14 ,  H01L21/823821 ,  H01L21/823828

Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.

Abstract translation: 公开了一种半导体器件。 半导体器件包括在第一方向上彼此平行并沿与第一方向正交的第二方向延伸的多个虚拟栅极线; 所述多个虚拟栅极线之间的多个第一虚拟填充图案，所述第一虚拟填充图案在所述第一方向上彼此平行，并且沿所述第二方向彼此分离布置; 多个第一虚拟填充图案中的多个第一虚拟通孔; 以及连接到所述多个第一虚拟通孔的多个第一虚拟布线，所述第一虚拟通路沿所述第二方向延伸，并且沿所述第一方向彼此平行。