ACTIVE SCHEDULING METHOD AND COMPUTING APPARATUS

    公开(公告)号:US20220171658A1

    公开(公告)日:2022-06-02

    申请号:US17327600

    申请日:2021-05-21

    Abstract: An active scheduling method performed with a master processor and a plurality of slave processors. The method includes determining whether a job to be performed has a dependency by referencing a job queue; in a case in which it is determined that the job to be performed has a dependency, updating a state of the job to be performed in a table in which information of each of a plurality of jobs is recorded; analyzing a state of a job preceding the job to be performed based on the table; and in a case in which the job preceding the job to be performed is determined to have been completed, performing the job to be performed by retrieving the job to be performed from the job queue.

    ELECTRONIC DEVICE, AND METHOD FOR PROVIDING PERSONALISED EXERCISE GUIDE THEREFOR

    公开(公告)号:US20190009136A1

    公开(公告)日:2019-01-10

    申请号:US16064159

    申请日:2016-12-26

    Abstract: A system for providing a personalised exercise guide according to various embodiments of the present invention may comprise: a wearable device for measuring a first bio-signal of a user using one or more sensors, and for transmitting to an electronic device and measured first bio-signal of the user; and the electronic device for receiving from the wearable device the measured first bio-signal of the user, for obtaining body data of the user based on the received first bio-signal of the user, for calculating a required quantity of exercise based on the obtained body data of the user and a preset goal, and for comparing and analyzing body data variation of the user that is estimated based on the calculated required quantity of exercise with the actual body data variation of the user due to exercise.

    SEMICONDUCTOR DEVICE
    3.
    发明公开

    公开(公告)号:US20240057320A1

    公开(公告)日:2024-02-15

    申请号:US18309144

    申请日:2023-04-28

    CPC classification number: H10B12/482 H10B12/0335 H10B12/315

    Abstract: A semiconductor device may include bit line structures extending in one direction on a substrate, insulation structures between the bit line structures and spaced apart from each other, and a landing pad structure in each of openings between the bit line structures and the insulation structures. The landing pad structure may include a first barrier metal pattern filling a portion of the opening, a second barrier metal pattern along a surface profile of the opening on the first barrier metal pattern, and a first metal pattern on the second barrier metal pattern. The second barrier metal pattern may have end portions on the bit line structures adjacent the opening. The first metal pattern may have an upper surface higher than an upper surface of the bit line structure. An uppermost surface of the first barrier metal pattern is lower than a lowermost surface of the first metal pattern.

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