公开(公告)号：US10666419B2

公开(公告)日：2020-05-26

申请号：US16108310

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Ha Kim ,  Hwa Seok Oh ,  Jin Hyeok Choi ,  Jang-Hoon Chun

IPC: H04L7/00 ,  H03K5/24 ,  H03G1/00 ,  H03F3/45

Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

公开(公告)号：US09348356B2

公开(公告)日：2016-05-24

申请号：US14025879

申请日：2013-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Pil Lee ,  Jin Hyeok Choi ,  Hwa Seok Oh ,  Young-Gyu Kang ,  Sung Ho Seo ,  Myung Sub Shin ,  Kyung Phil Yoo

IPC: G11C8/00 ,  G06F1/08 ,  G11C7/22 ,  G06F1/04 ,  G06F1/06

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/06 ,  G11C7/222

Abstract: An embedded multimedia card (eMMC) includes a clock channel that receives a clock signal from a host, a command channel that receives a command from the host, a plurality of data channels that transmit data to the host, and a return clock channel that transmits a return clock synchronized with the data to the host.

Abstract translation: 嵌入式多媒体卡（eMMC）包括从主机接收时钟信号的时钟信道，从主机接收命令的命令信道，向主机发送数据的多个数据信道以及发送数据的返回时钟信道 与数据同步的返回时钟到主机。

公开(公告)号：US20190280848A1

公开(公告)日：2019-09-12

申请号：US16108310

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Ha Kim ,  Hwa Seok Oh ,  Jin Hyeok Choi ,  Jung-Hoon Chun

IPC: H04L7/00 ,  H03F3/45 ,  H03G1/00 ,  H03K5/24

Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

公开(公告)号：US09430423B2

公开(公告)日：2016-08-30

申请号：US14025909

申请日：2013-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Phil Yoo ,  Jin Hyeok Choi ,  Seong Sik Hwang ,  Young Gyu Kang ,  Jung Pil Lee ,  Sung Ho Seo ,  Myung Sub Shin

IPC: G06F13/00 ,  G06F13/28 ,  G06K19/07 ,  G06K19/077

CPC classification number: G06F13/28 ,  G06K19/07 ,  G06K19/07732

Abstract: An eMMC includes flash memory including an extended card specific data (CSD) register (“EXT_CSD register”), and an eMMC controller that controls operation of the flash memory. The eMMC controller is receives a clock from a host via a clock line, receives a SEND_EXT_CSD command from the host via a command line, and provides the host with eMMC information stored in the EXT_CSD register via a data bus in response to the SEND_EXT_CSD command, the eMMC information including maximum operating frequency information for the eMMC.

Abstract translation: eMMC包括闪存，包括扩展卡特定数据（CSD）寄存器（“EXT_CSD寄存器”）和控制闪存的操作的eMMC控制器。 eMMC控制器通过时钟线从主机接收时钟，通过命令行从主机接收SEND_EXT_CSD命令，并通过SEND_EXT_CSD命令经由数据总线向主机提供存储在EXT_CSD寄存器中的eMMC信息， eMMC信息包括eMMC的最大工作频率信息。