公开(公告)号：US20210398908A1

公开(公告)日：2021-12-23

申请号：US17203312

申请日：2021-03-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ik Kyu JIN ,  Jin Su KIM ,  Ki Ju LEE

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

摘要： A semiconductor package includes a connection structure including a redistribution layer, a plurality of under bump metal layers electrically connected to the redistribution layer, a passivation layer which overlaps at least portions of side faces of the plurality of under bump metal layers, and includes a first trench disposed between under bump metal layers adjacent to each other, a surface mounting element which is on the under bump metal layers adjacent to each other, connected to the redistribution layer, and overlaps the first trench, and an underfill material layer that is between a portion of the passivation layer and the surface mounting element, and is in the first trench. The first trench extends in a first direction and includes a first sub-trench having a first width in a second direction, and a second sub-trench having a second width different from the first width in the second direction.

公开(公告)号：US20200035607A1

公开(公告)日：2020-01-30

申请号：US16282638

申请日：2019-02-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong Koon LEE ,  Jin Su KIM

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

摘要： A semiconductor package and an antenna module including the same includes a frame having first and second through-holes, a semiconductor chip disposed in the first through-hole of the frame and having an active surface on which a connection pad is disposed and an inactive surface disposed on an opposite side of the active surface, a wiring chip disposed in the second through-hole of the frame and including a body portion and a plurality of through vias penetrating the body portion, an encapsulant encapsulating at least portions of the semiconductor chip and the wiring chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and the through via of the wiring chip.

公开(公告)号：US20190371731A1

公开(公告)日：2019-12-05

申请号：US16149102

申请日：2018-10-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Myung Sam KANG ,  Jin Su KIM ,  Yong Jin PARK ,  Young Gwan KO ,  Yong Jin SEOL

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31

摘要： A semiconductor package includes a support member including a resin body having a first surface and a second surface opposing each other and having a cavity, and at least one passive component embedded in the resin body and having a connection terminal exposed from the first surface; a first connection member disposed on the first surface of the resin body, and having a first redistribution layer on the first insulating layer and connected to the connection terminal; a second connection member disposed on the first connection member and covering the cavity, and having a second redistribution layer on the second insulating layer and connected to the first redistribution layer; and a semiconductor chip disposed on the second connection member in the cavity.

公开(公告)号：US20200066662A1

公开(公告)日：2020-02-27

申请号：US16281819

申请日：2019-02-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong Koon LEE ,  Jin Su KIM

IPC分类号： H01L23/66 ,  H01L23/552 ,  H01L23/538 ,  H01L23/495 ,  H01Q1/22

摘要： A semiconductor package includes a frame having a first through-hole, a semiconductor chip having an active surface on which a connection pad is disposed; a first encapsulant encapsulating at least a portion of the semiconductor chip; a second encapsulant disposed on at least a portion of the external side surface of the frame, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip. The frame includes an insulating layer, a wiring layer disposed on upper and lower surfaces of the insulating layer, a first metal layer on the external side wall of the insulating layer, a second metal layer on the internal side wall of the first through hole, and a via penetrating the upper and lower surfaces of the insulating layer.

公开(公告)号：US20190287953A1

公开(公告)日：2019-09-19

申请号：US16170469

申请日：2018-10-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seon Hee MOON ,  Myung Sam KANG ,  Young Gwan KO ,  Chang Bae LEE ,  Jin Su KIM

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L23/053 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

摘要： A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.

公开(公告)号：US20180136554A1

公开(公告)日：2018-05-17

申请号：US15606170

申请日：2017-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Ji Beom YOO ,  Sung Won KWON ,  Dong Wook SHIN ,  Mun Ja KIM ,  Jin Su KIM ,  Hwan Chul JEON

IPC分类号： G03F1/62 ,  H01L21/027 ,  G03F1/80 ,  G03F7/20

CPC分类号： G03F1/62 ,  G03F1/22 ,  G03F1/80 ,  G03F7/2004 ,  H01L21/0274

摘要： A method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing EUV light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer. The forming the support includes etching the first region of the substrate and the first dielectric layer on the first region.