公开(公告)号：US08946077B2

公开(公告)日：2015-02-03

申请号：US14158223

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US10797056B2

公开(公告)日：2020-10-06

申请号：US16749791

申请日：2020-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Joo-Young Lee ,  Cha-Won Koh ,  Yeong-Cheol Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3065

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, buried semiconductor layers, a word line, a bit line, buried contacts, and insulation spacers, and a charge storage. The substrate has active regions and field regions. The buried semiconductor layers are buried in the substrate at the active regions. The word line is buried in the substrate and crosses one of the active regions. The bit line is disposed in one of the active regions. The buried contacts are disposed on the active regions and the field regions. The insulation spacers are disposed on the substrate and on a sidewall of the buried contacts, respectively. The charge storage is disposed on one or more of the buried contacts. The buried semiconductor layers contact, respectively, one of the buried contacts and one of the insulation spacers.

公开(公告)号：US20140206186A1

公开(公告)日：2014-07-24

申请号：US14158223

申请日：2014-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US11152374B2

公开(公告)日：2021-10-19

申请号：US16171517

申请日：2018-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Jung-Woo Song ,  Joo-Young Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor device includes a bit line structure on a substrate, a spacer structure including a first spacer directly contacting a sidewall of the bit line structure, a second spacer directly contacting a portion of an outer sidewall of the first spacer, the second spacer including air, and a third spacer directly contacting an upper portion of the first spacer and covering an outer sidewall and an upper surface of the second spacer, and a contact plug structure extending in a vertical direction substantially perpendicular to an upper surface of the substrate and directly contacting an outer sidewall of the third spacer at least at a height between respective heights of a bottom and a top surface of the second spacer.

公开(公告)号：US10586798B2

公开(公告)日：2020-03-10

申请号：US16170665

申请日：2018-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-A Kim ,  Yong-Kwan Kim ,  Se-Keun Park ,  Joo-Young Lee ,  Cha-Won Koh ,  Yeong-Cheol Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/285

Abstract: A semiconductor device and methods of manufacturing the same are provided. The semiconductor device includes a substrate, word lines, a doped junction, bit line structures, and buried contacts. The substrate has active regions. The word lines extend across the active regions. The doped junction has impurities and is arranged at the active regions, and includes first junctions and second junctions, each first junction arranged at a central portion of one of the active regions and each second junction arranged at an end portion of another one of the active regions, a buried semiconductor layer being included in each second junction. The bit line structures contact with a respective one of the first junctions. The buried contacts are arranged in a matrix shape, each contacting with a respective one of the second junctions and the included buried semiconductor layer and simultaneously contacting with a charge storage for storing data.