公开(公告)号：US20190139963A1

公开(公告)日：2019-05-09

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo HONG ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L23/535 ,  H01L21/768

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US08946077B2

公开(公告)日：2015-02-03

申请号：US14158223

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US09508649B2

公开(公告)日：2016-11-29

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US20160211215A1

公开(公告)日：2016-07-21

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/423 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US10886277B2

公开(公告)日：2021-01-05

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US11574912B2

公开(公告)日：2023-02-07

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US20140206186A1

公开(公告)日：2014-07-24

申请号：US14158223

申请日：2014-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。