公开(公告)号：US10586584B2

公开(公告)日：2020-03-10

申请号：US16228518

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US20140206186A1

公开(公告)日：2014-07-24

申请号：US14158223

申请日：2014-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US11557332B2

公开(公告)日：2023-01-17

申请号：US17322227

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US11031065B2

公开(公告)日：2021-06-08

申请号：US17024259

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US08946077B2

公开(公告)日：2015-02-03

申请号：US14158223

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US10811078B2

公开(公告)日：2020-10-20

申请号：US16779194

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

IPC: G01C7/00 ,  G11C11/406 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

公开(公告)号：US09184091B2

公开(公告)日：2015-11-10

申请号：US14101631

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young Song ,  Cheol-Ju Yun ,  Seung-Hee Ko ,  Jina Kim ,  Hyun-Gi Kim ,  Chae-Ho Lim

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract translation: 第一掺杂区域和第二掺杂剂区域设置在栅极结构的两侧。 导电线在栅极结构上交叉并连接到第一掺杂区。 每个导线包括导电图案和设置在导电图案上的封盖图案。 在导线之间提供接触结构，并连接到第二掺杂剂区域。 每个接触结构包括设置在第二掺杂剂区域上的下接触图案和设置在下接触图案上的上接触图案。 上触点图案的底表面低于导电图案的顶表面。