公开(公告)号：US09184091B2

公开(公告)日：2015-11-10

申请号：US14101631

申请日：2013-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo-Young Song ,  Cheol-Ju Yun ,  Seung-Hee Ko ,  Jina Kim ,  Hyun-Gi Kim ,  Chae-Ho Lim

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L21/7682 ,  H01L21/76831 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

Abstract: First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern.

Abstract translation: 第一掺杂区域和第二掺杂剂区域设置在栅极结构的两侧。 导电线在栅极结构上交叉并连接到第一掺杂区。 每个导线包括导电图案和设置在导电图案上的封盖图案。 在导线之间提供接触结构，并连接到第二掺杂剂区域。 每个接触结构包括设置在第二掺杂剂区域上的下接触图案和设置在下接触图案上的上接触图案。 上触点图案的底表面低于导电图案的顶表面。

公开(公告)号：US20140206186A1

公开(公告)日：2014-07-24

申请号：US14158223

申请日：2014-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。

公开(公告)号：US09343355B2

公开(公告)日：2016-05-17

申请号：US14197729

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chae-Ho Lim ,  Bo-Young Song ,  Cheol-Ju Yun

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer.

Abstract translation: 制造布线结构的方法可以包括在基板上形成第一导电图案，在第一导电图案上形成硬掩模，在第一导电图案和硬掩模的侧壁上形成第一间隔物，在第一导电图案上形成第一牺牲层图案 可以提供第一间隔物的侧壁，在第一牺牲层图案的侧壁上形成第二间隔物，去除第一牺牲层图案，以及在第二间隔物上形成第三间隔物。 第三间隔件可以接触第一间隔件的侧壁的上部并且与第一和第二间隔件相关联地限定空气间隙。 第一间隔物的顶表面基本上高于第一导电图案的顶表面。 第二间隔件具有基本上比第一间隔件的顶表面低的顶表面。

公开(公告)号：US08946077B2

公开(公告)日：2015-02-03

申请号：US14158223

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Bo-Young Song ,  Seung-Hee Ko ,  Jin-A Kim ,  Hyun-Gi Kim ,  Cheol-Ju Yun ,  Chae-Ho Lim

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76837 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.

Abstract translation: 一种制造半导体器件的方法包括：通过细长的孔在第一方向上形成彼此分离的多个导线，并沿与第一方向垂直的第二方向延伸，形成填充多个之间的细长孔的第一绝缘层 的导线，通过对第一绝缘层进行图案化，形成在第一方向和第二方向上在多个导线之间彼此分离的多个第一隔离孔，在第一隔离孔中形成衬垫层，填充第二绝缘体 在衬垫层的第一隔离孔中具有相对于第一绝缘层的蚀刻选择性的层，并且通过使用第二绝缘层和第二绝缘层之间的蚀刻选择性去除第一绝缘层，在导电线之间形成多个第二隔离孔 第一绝缘层。