公开(公告)号：US20230187519A1

公开(公告)日：2023-06-15

申请号：US17896523

申请日：2022-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyung SON ,  Seungje KIM ,  Jiwon PARK ,  Jaepo LIM ,  Minseok JO ,  Seunghyun LIM ,  Jinyoung CHOI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with an active region extending in a first direction; an element isolation layer, adjacent to the active region, in the substrate; a gate electrode on the substrate and extending in a second direction which crosses the first direction; a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode; and a source/drain region provided in a recess of the active region adjacent to the gate electrode, and connected to the plurality of channel layers. In the first direction, the gate electrode has a first length on the active region and a second length, greater than the first length, on the element isolation layer.

公开(公告)号：US20240313077A1

公开(公告)日：2024-09-19

申请号：US18537536

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsung KIM ,  Yeonghan GWON ,  Jinkyung SON ,  Jaepo LIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.