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公开(公告)号:US20250124995A1
公开(公告)日:2025-04-17
申请号:US18639033
申请日:2024-04-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Buil Nam , Jinsun Yeom
Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a row decoder configured to select one of the plurality of wordlines in response to an address, and a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation, wherein the trim information is stored internally in an electrical die sorting (EDS) process.
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公开(公告)号:US11915773B2
公开(公告)日:2024-02-27
申请号:US17693571
申请日:2022-03-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyunghae Lee , Buil Nam , Jinsun Yeom , Sangwan Nam , Jaein Lee
CPC classification number: G11C29/38 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C29/12005
Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a voltage path circuit and a wordline defect detection circuit. The memory cell array includes memory cells and wordlines connected to the memory cells. The voltage generator generates a wordline voltage applied to the wordlines. The voltage path circuit between the voltage generator and the memory cell array transfers the wordline voltage to the wordlines. The wordline defect detection circuit is connected to a measurement node between the voltage generator and the voltage path circuit. The wordline defect detection circuit measures a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode and determines defect of each wordline of the wordlines based on the offset value and the measurement voltage in a defect detection mode.
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