公开(公告)号：US20190312755A1

公开(公告)日：2019-10-10

申请号：US16316687

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-Ho KIM ,  Taesin SONG ,  Jinyong JANG

IPC: H04L25/02 ,  H04L25/49

Abstract: Various embodiments of the present invention relate to an apparatus and a method for transmitting data between internal modules in an electronic device. Here, a transmission apparatus of a digital interface may comprise: multiple transmission lines connected to a reception apparatus; and multiple transmission circuits connected in parallel to each other and provided for each of the transmission lines, wherein the transmission apparatus may be configured to transmit data having different voltages to the reception apparatus, using at least one transmission circuit among the multiple transmission circuits for each of the transmission lines on the basis of a variation of the voltage of data to be transmitted through each of the transmission lines. Other embodiments are also possible.

公开(公告)号：US20150261683A1

公开(公告)日：2015-09-17

申请号：US14643046

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok HONG ,  Byoungik KANG ,  Gilyoon KIM ,  Jinyoung PARK ,  Seungjin YANG ,  Jinyong JANG ,  Chunmok CHUNG ,  Jin CHOI

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0895

Abstract: Disclosed are a method and apparatus for controlling a cache memory in an electronic device. The apparatus includes a cache memory having cache lines, each of which includes tag information and at least two sub-lines. Each of the at least two sub-lines including a valid bit and a dirty bit. A control unit may analyze a valid bit of a sub-line corresponding to an address tag of data when a request for writing the data is sensed, determine based on activation or deactivation of the valid bit whether a cache hit or a cache miss occurs, and perform a control operation for allocating a sub-line according to a size of the requested data and write the data when the cache hit occurs.

Abstract translation: 公开了一种用于控制电子设备中的高速缓冲存储器的方法和装置。 该装置包括具有高速缓存行的高速缓冲存储器，每个高速缓存行包括标签信息和至少两个子行。 所述至少两条子线中的每一条包括有效位和脏位。 当感测到写入数据的请求时，控制单元可以分析对应于数据的地址标签的子线的有效位，基于是否发生高速缓存命中或高速缓存未命中来确定有效位的激活或去激活， 并且执行用于根据所请求数据的大小分配子行的控制操作，并且在发生高速缓存命中时写入数据。