公开(公告)号：US20130246582A1

公开(公告)日：2013-09-19

申请号：US13792878

申请日：2013-03-11

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Heungki LEE ,  Seungseok HONG ,  Gilyoon KIM ,  Seunghwan JEONG

IPC: H04L29/08

CPC classification number: H04L67/02 ,  H04N21/23439 ,  H04N21/44209 ,  H04N21/4621 ,  H04N21/6373 ,  H04N21/6375 ,  H04N21/658 ,  H04N21/6587

Abstract: The data download method of a terminal device processing data downloaded in progressive download mode is provided. The method includes measuring bandwidth of the data downloaded, requesting, when the measured bandwidth is narrower than a reference bandwidth, for transmitting data with narrow bandwidth, registering a duration in which the data is downloaded with narrow bandwidth as a backup duration, requesting, when the measured bandwidth is equal to or greater than the reference bandwidth, for retransmission of backup data corresponding to the backup duration through a backup channel, and storing the data of the backup duration.

Abstract translation: 提供处理以逐行下载模式下载的数据的终端设备的数据下载方法。 该方法包括测量下载的数据的带宽，当测量的带宽比参考带宽窄时，为了发送带宽窄的数据，请注册以窄带宽下载数据的持续时间作为备用持续时间，请求，何时 测量带宽等于或大于参考带宽，用于通过备用信道重传与备份持续时间相对应的备份数据，并存储备份持续时间的数据。

公开(公告)号：US20150261683A1

公开(公告)日：2015-09-17

申请号：US14643046

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok HONG ,  Byoungik KANG ,  Gilyoon KIM ,  Jinyoung PARK ,  Seungjin YANG ,  Jinyong JANG ,  Chunmok CHUNG ,  Jin CHOI

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0895

Abstract: Disclosed are a method and apparatus for controlling a cache memory in an electronic device. The apparatus includes a cache memory having cache lines, each of which includes tag information and at least two sub-lines. Each of the at least two sub-lines including a valid bit and a dirty bit. A control unit may analyze a valid bit of a sub-line corresponding to an address tag of data when a request for writing the data is sensed, determine based on activation or deactivation of the valid bit whether a cache hit or a cache miss occurs, and perform a control operation for allocating a sub-line according to a size of the requested data and write the data when the cache hit occurs.

Abstract translation: 公开了一种用于控制电子设备中的高速缓冲存储器的方法和装置。 该装置包括具有高速缓存行的高速缓冲存储器，每个高速缓存行包括标签信息和至少两个子行。 所述至少两条子线中的每一条包括有效位和脏位。 当感测到写入数据的请求时，控制单元可以分析对应于数据的地址标签的子线的有效位，基于是否发生高速缓存命中或高速缓存未命中来确定有效位的激活或去激活， 并且执行用于根据所请求数据的大小分配子行的控制操作，并且在发生高速缓存命中时写入数据。