公开(公告)号：US20170186481A1

公开(公告)日：2017-06-29

申请号：US15262183

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min OH ,  Ho-Young SONG

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G11C11/406

Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

公开(公告)号：US20140104921A1

公开(公告)日：2014-04-17

申请号：US14049399

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min YU ,  Sung-Min SEO ,  Ho-Young SONG ,  Gil-Su KIM ,  Jong-Min OH

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。

公开(公告)号：US20170011792A1

公开(公告)日：2017-01-12

申请号：US15134637

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min OH ,  Ho-Young SONG ,  Do-Yeon KIM

IPC: G11C11/406 ,  G11C7/10

Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

Abstract translation: 提供包括在内存设备和包括嵌入式刷新控制器的存储设备中的嵌入式刷新控制器。 嵌入式刷新控制器可以包括刷新计数器和地址生成器。 刷新计数器可以响应于计数器刷新信号而生成计数器刷新地址信号，使得计数器刷新地址信号可以表示顺序变化的地址。 地址生成器可以存储关于密集访问的音锤地址的信息，并且可以响应于音锤刷新信号而产生音锤刷新地址信号，使得音锤刷新地址信号可以表示与物理上相邻的行的地址 一排锤子地址。 可以通过检测集中访问的锤地址并且基于检测到的锤地址有效地执行刷新操作，可以减少存储器件的损耗并且可以提高存储器件的性能。