公开(公告)号：US20160197603A1

公开(公告)日：2016-07-07

申请号：US14847076

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gil-Su KIM

IPC: H03K17/14 ,  H03K19/20

CPC classification number: H03K19/20 ,  H03K19/00346

Abstract: A decoupling circuit and a semiconductor device including the same are provided. The decoupling circuit includes a first circuit including a first capacitor having a first end connected to a first terminal, a first switch device connected between a second end of the first capacitor and a second terminal, and a first control device configured to turn on/off the first switch device based on a voltage level of the a second end of the first capacitor, and a second circuit including a second capacitor having a first end connected to the first terminal, a second switch device connected between a second end of the second capacitor and the second terminal, and a second control device configured to turn on/off the second switch device based on a voltage level of the second end of the second capacitor and an output signal of the first control device.

Abstract translation: 提供了一种去耦电路和包括该解耦电路的半导体器件。 去耦电路包括第一电路，第一电路包括第一电容器，第一电容器具有连接到第一端子的第一端子，连接在第一电容器的第二端和第二端子之间的第一开关装置和被配置为接通/断开的第一控制装置 所述第一开关装置基于所述第一电容器的第二端的电压电平，以及第二电路，包括具有连接到所述第一端子的第一端的第二电容器;第二开关装置，连接在所述第二电容器的第二端 和第二端子，以及第二控制装置，其被配置为基于第二电容器的第二端的电压电平和第一控制装置的输出信号来接通/断开第二开关装置。

公开(公告)号：US20150325316A1

公开(公告)日：2015-11-12

申请号：US14595500

申请日：2015-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Gil-Su KIM ,  Je-Min RYU ,  Yun-Young LEE ,  Kyo-Min SOHN

IPC: G11C29/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。

公开(公告)号：US20140104921A1

公开(公告)日：2014-04-17

申请号：US14049399

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min YU ,  Sung-Min SEO ,  Ho-Young SONG ,  Gil-Su KIM ,  Jong-Min OH

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。