SEMICONDUCTOR DEVICE
    1.
    发明申请

    公开(公告)号:US20180005943A1

    公开(公告)日:2018-01-04

    申请号:US15704049

    申请日:2017-09-14

    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

    SEMICONDUCTOR DEVICE
    2.
    发明申请

    公开(公告)号:US20190027438A1

    公开(公告)日:2019-01-24

    申请号:US16119475

    申请日:2018-08-31

    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

    INTEGRATED CIRCUIT DEVICES
    3.
    发明申请

    公开(公告)号:US20220085011A1

    公开(公告)日:2022-03-17

    申请号:US17410326

    申请日:2021-08-24

    Abstract: An integrated circuit device includes substrate including a fin-type active area extending on the substrate in a first direction parallel to an upper surface of the substrate, a first gate line crossing the fin-type active area on the substrate and extending in a second direction perpendicular to the first direction, a cut gate line extending in the second direction and being spaced apart from the first gate line with a first gate cut area therebetween, a second gate line extending in the second direction and being spaced apart from the cut gate line with a second gate cut area therebetween, and a power wiring disposed on the cut gate line.

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