公开(公告)号：US20240023336A1

公开(公告)日：2024-01-18

申请号：US18212323

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Seungje Oh ,  Joohang Lee

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: The present disclosure provides for apparatuses and systems including integrated circuit devices. In some embodiments, an integrated circuit device includes a semiconductor substrate including a memory cell area and a connection area, a gate stack including a plurality of word line gate layers and a plurality of insulating layers and having a step structure in the connection area, a word line cut region passing through the plurality of word line gate layers in the memory cell area and the connection area and extending in a third direction, a plurality of first channel structures disposed on the memory cell area, a string select line gate layer disposed on the gate stack in the memory cell area, a plurality of second channel structures passing through the string select line gate layer, and a string select line cut region passing through the string select line gate layer.