公开(公告)号：US11985820B2

公开(公告)日：2024-05-14

申请号：US17348172

申请日：2021-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Jaehoon Shin ,  Dongseog Eun ,  Geunwon Lim

IPC: H10B41/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.

公开(公告)号：US11430808B2

公开(公告)日：2022-08-30

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Beyounghyun Koh ,  Yongjin Kwon ,  Kangmin Kim ,  Jaehoon Shin ,  JoongShik Shin ,  Sungsoo Ahn ,  Seunghwan Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

公开(公告)号：US11362105B2

公开(公告)日：2022-06-14

申请号：US16902489

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Kangmin Kim ,  Joongshik Shin ,  Geunwon Lim

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US20240023336A1

公开(公告)日：2024-01-18

申请号：US18212323

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Seungje Oh ,  Joohang Lee

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: The present disclosure provides for apparatuses and systems including integrated circuit devices. In some embodiments, an integrated circuit device includes a semiconductor substrate including a memory cell area and a connection area, a gate stack including a plurality of word line gate layers and a plurality of insulating layers and having a step structure in the connection area, a word line cut region passing through the plurality of word line gate layers in the memory cell area and the connection area and extending in a third direction, a plurality of first channel structures disposed on the memory cell area, a string select line gate layer disposed on the gate stack in the memory cell area, a plurality of second channel structures passing through the string select line gate layer, and a string select line cut region passing through the string select line gate layer.

公开(公告)号：US20220139952A1

公开(公告)日：2022-05-05

申请号：US17370507

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C7/18 ,  H01L23/522

Abstract: A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads.

公开(公告)号：US20250098170A1

公开(公告)日：2025-03-20

申请号：US18968053

申请日：2024-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Kyeong Jin Park ,  Seulji Lee ,  Hyejin Lee

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming a mold structure, in which sacrificial layers and insulating layers are alternately stacked, on a substrate; forming trenches to penetrate the mold structure; forming first sacrificial patterns in the trenches; forming a first supporting layer on the mold structure and the first sacrificial patterns; forming vertical structures to penetrate the first supporting layer and the mold structure; forming a second supporting layer on the first supporting layer and on the vertical structures; forming openings to penetrate the first and second supporting layers and to expose the first sacrificial patterns; removing the first sacrificial patterns through the openings; and replacing the sacrificial layers with electrodes.

公开(公告)号：US12185534B2

公开(公告)日：2024-12-31

申请号：US17649562

申请日：2022-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Byunggon Park ,  Seungmin Lee ,  Kangmin Kim ,  Taemin Eom ,  Byungkwan You

IPC: H10B41/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/60 ,  H01L27/02 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: An integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.

公开(公告)号：US12058859B2

公开(公告)日：2024-08-06

申请号：US17174497

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Joongshik Shin ,  Hongik Son ,  Hyeonjoo Song

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.

公开(公告)号：US20230005949A1

公开(公告)日：2023-01-05

申请号：US17720453

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Lee ,  Kangmin Kim ,  Junhyoung Kim ,  Yonghoon Son ,  Joonsung Lim

IPC: H01L27/11575 ,  H01L23/535 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.

公开(公告)号：US20210399009A1

公开(公告)日：2021-12-23

申请号：US17174497

申请日：2021-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangmin Kim ,  Joongshik Shin ,  Hongik Son ,  Hyeonjoo Song

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.