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公开(公告)号：US20250157959A1
公开(公告)日：2025-05-15
申请号：US18662536
申请日：2024-05-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joon MOON , Younghwan SON , Sukkang SUNG
IPC: H01L23/00
Abstract: A semiconductor device may include a circuit element wire, a lower wire connected to the circuit element wire, a lower interlayer insulation layer on the lower wire, and a first contact pad penetrating the lower interlayer insulation layer. The first contact pad may include a first portion connected to the lower wire, a second portion including a void on the first portion, and a third portion on the second portion. A maximum width between both outer surfaces of the second portion along a horizontal direction may be larger than a width of the third portion along the horizontal direction.
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公开(公告)号：US20250151272A1
公开(公告)日：2025-05-08
申请号：US18746736
申请日：2024-06-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joon MOON , Young Hwan SON , Shin Hwan KANG , Suk Kang SUNG
Abstract: Semiconductor memory devices including memory cells arranged three-dimensionally, methods for fabricating the same, and electronic systems including the same are provided. The semiconductor memory device includes a first stacked structure including first gate electrodes sequentially stacked and spaced apart from each other, a second stacked structure on the first stacked structure and including second gate electrodes sequentially stacked and spaced apart from each other, and a channel structure extending in a vertical direction and passing through the first and second stacked structures, wherein the channel structure includes a channel layer including a first pillar portion crossing the first gate electrodes, a second pillar portion crossing the second gate electrodes, and a horizontal portion extending along a plane crossing the vertical direction, the horizontal portion connecting the first and second pillar portions, and a data storage layer extending along an outer side of the channel layer.
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