公开(公告)号：US20240397719A1

公开(公告)日：2024-11-28

申请号：US18791831

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US12058863B2

公开(公告)日：2024-08-06

申请号：US18158605

申请日：2023-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H01L27/11582 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US20230165005A1

公开(公告)日：2023-05-25

申请号：US18158605

申请日：2023-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H10B43/27 ,  G11C8/14 ,  H01L23/522 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H01L23/5226 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US20210265389A1

公开(公告)日：2021-08-26

申请号：US17037074

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

公开(公告)号：US10402620B2

公开(公告)日：2019-09-03

申请号：US15981311

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ho Kim ,  Da Hee Kim ,  Joon Sung Kim ,  Joo Young Choi ,  Hee Sook Park ,  Tae Wook Kim

IPC: G06K9/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/053 ,  H01L23/055 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

公开(公告)号：US11778821B2

公开(公告)日：2023-10-03

申请号：US17037074

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11575 ,  H10B43/27 ,  G11C8/14 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.